X28C512DMB-20 データシートの表示（PDF） - Intersil

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X28C512DMB-20

5V, Byte Alterable EEPROM

Intersil 

Block Diagram

A7-A15

X28C512, X28C513

X Buffers

Latches and

Decoder

512Kbit

EEPROM

Array

A0-A6

Y Buffers

Latches and

Decoder

I/O Buffers

and Latches

Ordering Information

PART NUMBER

X28C512D

X28C512DM

X28C512J

X28C513EM

X28C512D-12

X28C512DI-12

X28C512DMB-12

X28C512FMB-12

X28C512J-12*

X28C512JZ-12* (See Note)

X28C512JI-12

X28C512JIZ-12* (See Note)

X28C512JM-12

X28C512KM-12

X28C512PI-12

X28C512RMB-12

X28C513EM-12

X28C513EMB-12

X28C513J-12*

X28C513JZ-12* (Note)

X28C513JI-12*

X28C513JIZ-12* (Note)

X28C513JM-12

CE

OE

WE

VCC

VSS

Control

Logic and

Timing

I/O0-I/O7

Data Inputs/Outputs

PART MARKING

X28C512D

X28C512DM

X28C512J

X28C513EM

X28C512D-12

X28C512DI-12

X28C512DMB-12

X28C512FMB-12

X28C512J-12

X28C512J-12 Z

X28C512JI-12

X28C512JI-12 Z

X28C512JM-12

X28C512KM-12

X28C512PI-12

X28C512RMB-12

X28C513EM-12

X28C513EMB-12

X28C513J-12

X28C513J-12 Z

X28C513JI-12

X28C513JI-12 Z

X28C513JM-12

ACCESS TIME

(ns)

-

120

TEMP RANGE (°C)

0 to +70

-55 to +125

0 to +70

-55 to +125

0 to +70

-40 to +85

Mil-STD-883

Mil-STD-883

0 to +70

0 to +70

-40 to +85

-40 to +85

-55 to +125

-55 to +125

-40 to +85

Mil-STD-883

-55 to +125

Mil-STD-883

0 to +70

0 to +70

-40 to +85

-40 to +85

-55 to +125

PACKAGE

32 Ld CERDIP

32 Ld CERDIP

32 Ld PLCC

32 Ld LCC

32 Ld CERDIP

32 Ld CERDIP

32 Ld CERDIP

32 Ld Flat Pack

32 Ld PLCC

32 Ld PLCC (Pb-free)

32 Ld PLCC

32 Ld PLCC (Pb-free)

32 Ld PLCC

36 Ld CPGA

32 Ld PDIP

32 Ld Flat Pack

32 Ld LCC

32 Ld LCC

32 Ld PLCC

32 Ld PLCC (Pb-free)

32 Ld PLCC

32 Ld PLCC (Pb-free)

32 Ld PLCC

2

FN8106.2

June 7, 2006

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