X28HC256 データシートの表示（PDF） - Xicor -> Intersil
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X28HC256 Datasheet PDF : 24 Pages
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X28HC256
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
VOH
I/O6
*
VOL
* I/O6 beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
HIGH Z
*
X28HC256
READY
3859 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently up-
dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
NO
OK?
YES
X28HC256
READY
3859 FHD F15
5
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