X5001 データシートの表示（PDF） - Xicor -> Intersil

部品番号

コンポーネント説明

メーカー

X5001

CPU Supervisor

Xicor -> Intersil 

X5001

Figure 3. Write Watchdog Timer Sequence

CS

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

INSTRUCTION

SI

SO

HIGH IMPEDANCE

DATA BYTE

6 54 3

WW

DD

10

Figure 4. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation)

CS

SCK

01234567

RWDT

INSTRUCTION

SI

NONVOLATILE WRITE IN PROGRESS

SO

SO HIGH During 1st bit while

in the Nonvolatile write cycle

Figure 5. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation)

CS

SCK

SI

SO

01234567

RWDT

INSTRUCTION

NONVOLATILE WRITE IN PROGRESS

SO HIGH During

Nonvolatile write cycle

8

Share Link: