ICX080AK データシートの表示（PDF） - Sony Semiconductor
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ICX080AK Datasheet PDF : 19 Pages
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ICX080AK
Block Diagram and Pin Configuration
(Top View)
8
7
65
4
3
2
1
Cy
Ye
Cy
Mg
G
Mg
Cy
Ye
Cy
G
Mg
G
Cy
Ye
Cy
Mg
G
Mg
Horizontal Register
Ye
G
Ye
Mg
Ye
G Note)
Note)
9 10 11 12 13 14 15 16
: Photo sensor
Pin Description
Pin No. Symbol
Description
1 Vφ4
Vertical register transfer clock
2 Vφ3
Vertical register transfer clock
3 Vφ2
Vertical register transfer clock
4 Vφ1
Vertical register transfer clock
Pin No. Symbol
Description
9
VDD
Supply voltage
10 GND GND
11 φSUB Substrate clock
12 CSUB Substrate bias ∗1
5 GND GND
13 VL
Protective transistor bias
6 GND GND
14 φRG Reset gate clock
7 GND GND
15 Hφ1
Horizontal register transfer clock
8 VOUT Signal output
16 Hφ2
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Absolute Maximum Ratings
Item
VDD, VOUT, φRG – φSUB
Vφ1, Vφ3 – φSUB
Against φSUB
Vφ2, Vφ4, VL – φSUB
Hφ1, Hφ2, GND – φSUB
CSUB – φSUB
VDD, VOUT, φRG, CSUB – GND
Against GND
Vφ1, Vφ2, Vφ3, Vφ4 – GND
Hφ1, Hφ2 – GND
Against VL
Vφ1, Vφ3 – VL
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
Between input clock
pins
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ4
Storage temperature
Operating temperature
∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Ratings Unit Remarks
–40 to +10 V
–50 to +15 V
–50 to +0.3 V
–40 to +0.3 V
–25 to
V
–0.3 to +18 V
–10 to +18 V
–10 to +5 V
–0.3 to +28 V
–0.3 to +15 V
to +15
V
∗2
–5 to +5 V
–13 to +13 V
–30 to +80 °C
–10 to +60 °C
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