XC9572 データシートの表示（PDF） - Xilinx Inc
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XC9572 Datasheet PDF : 8 Pages
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XC9572 In-System Programmable CPLD
Internal Timing Parameters
Symbol
Parameter
XC9572-7 XC9572-10
Min Max Min Max
Buffer Delays
tIN
Input buffer delay
tGCK
GCK buffer delay
tGSR
GSR buffer delay
tGTS
GTS buffer delay
tOUT
Output buffer delay
tEN
Output buffer enable/disable delay
Product Term Control Delays
tPTCK
Product term clock delay
tPTSR
Product term set/reset delay
tPTTS
Product term 3-state delay
Internal Register and Combinatorial delays
tPDI
Combinatorial logic propagation delay
tSUI
Register setup time
1.5
tHI
Register hold time
3.0
tCOI
Register clock to output valid time
tAOI
Register async. S/R to output delay
tRAI
Register async. S/R recovery before clock 7.5
tLOGI
Internal logic delay
tLOGILP Internal low power logic delay
Feedback Delays
tF
FastCONNECT matrix feedback delay
tLF
Function Block local feeback delay
Time Adders
tPTA3
tSLEW
Incremental Product Term Allocator delay
Slew-rate limited delay
2.5
3.5
1.5
2.5
4.5
6.0
5.5
6.0
2.5
3.0
0.0
0.0
3.0
3.0
2.0
2.5
4.5
3.5
0.5
1.0
2.5
3.5
0.5
0.5
6.5
7.0
10.0
2.0
2.5
10.0
11.0
8.0
9.5
4.0
3.5
1.0
1.0
4.0
4.5
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
XC9572-15
Units
Min Max
4.5 ns
3.0 ns
7.5 ns
11.0 ns
4.5 ns
0.0 ns
2.5 ns
3.0 ns
5.0 ns
3.0 ns
3.5
ns
4.5
ns
0.5 ns
8.0 ns
10.0
ns
3.0 ns
11.5 ns
11.0 ns
3.5 ns
1.0 ns
5.0 ns
December 4, 1998 (Version 3.0)
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