SAA8110G/C1 データシートの表示（PDF） - Philips Electronics
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SAA8110G/C1 Datasheet PDF : 36 Pages
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Philips Semiconductors
Digital Signal Processor (DSP) for
cameras
Preliminary specification
SAA8110G
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
CDAC specification (VDD = 5 V)
Lint
Ldiff
Vo(CDAC)
integral linearity
differential linearity
output voltage at pin CDAC
Ro(CDAC)
fclk
RL
CL
tPD
output resistance at pin CDAC
clock frequency
load resistance
load capacitance
propagation delay time
tst(10-90)
settling time
−
−
code 0
−
code 61, VDDA = 5 V
−4.6
code 61, VDDA = 3.3 V
3
−
−
−
−
to 50% value (see Fig.17), −
VDDA = 5 V
10% to 90% full-scale (see −
Fig.16)
−
−
10
4.95
3.25
13
28.6
10
−
−
9
tst(LSB)
setting time
to ±1 LSB (see Fig.16)
−
25
INPUTS RELATED TO CLK1: CCD0 TO CCD9, VSYNCIN, HSYNCIN, FIIN
tsu(i)(D)1
data input set-up time CCD
inputs, HSYNCIN, VSYNCIN, FIIN
0
3
tsu(i)(D)2
data input set-up time SNRES and
SNDA
0
1
th(i)(CCD) data hold time CCD inputs
−1
−
th(i)(D)
data input hold time
VSYNCIN, HSYNCIN, FIIN
0
1
OUTPUTS RELATED TO CLK2: Y7 TO Y0, UV7 TO UV0, CREF, HREF, VSYNCOUT, FIOUT AND LLC
th(o)(D)
td(o)(D)
data output hold time
data output delay time
−
8
−
25
OUTPUTS RELATED TO CLK1: SDATA, STROBE, SMP, P0, P1 AND SCLK
th(o)(D)
td(o)(D)
δclk
data output hold time
data output delay time
clock duty cycle
−
13
−
15
40
−
Notes
1. When CVBS output is used the chrominance range is halved compared to luminance.
2. Monitor load of 75 Ω with Rext = 21 Ω and Rbias = 15 kΩ at 3.3 V application.
3. Monitor load of 75 Ω with Rext = 70.6 Ω and Rbias = 47 kΩ at 5.0 V application.
MAX.
1
1⁄2
300
−
−
−
−
−
10
104
−
−
5
2
+1
3
22
31
21
24
60
UNIT
LSB
LSB
mV
V
V
Ω
MHz
kΩ
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
1997 Jun 13
18
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