RF109 データシートの表示（PDF） - Conexant Systems
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RF109 Datasheet PDF : 12 Pages
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2400 MHz Digital Spread Spectrum Transceiver
Synthesizer Programming____________________________
The frequency synthesizer block is comprised of a divide-by-3
counter (D), 9.6 MHz reference frequency (FREF) source, a
fixed reference divider of 16 (R), 16/17 prescaler (M), a fixed
counter of 83 (N), a programmable counter of 64 (A),an external
loop filter, and a 2.4 GHz external VCO.
The synthesizer can be programmed to cover 64 channels
(channel spacing = 1.8 MHz) from 2392.2 MHz to 2505.6 MHz
Table 1).
The LO frequency is given by the following equation:
fLO = (D) × (FREF/R) × ((M × N) + (A + 1)), where N > A.
Example:
fLO = 3 × (9.6 MHz / 16) × ((16 × 83) + 7) = 2403.0 MHz
fLO = 3 × (9.6 MHz / 16) × ((16 × 83) + 46) = 2473.2 MHz
Data Format. The synthesizer is programmed with a half-
duplex 3-wire serial interface. The three signals are DATA, CLK,
and STROBE. Each rising edge of the CLK signal shifts one bit
of the data into a shift register. When the STROBE input is
toggled from low to high, the data latched in the shift register is
transferred to the A counter. The data format is as follows:
MSB S7 S6 S5 S4 S3 S2 S1 S0 LSB
The timing relationship is shown in Figure 4. Programming bits
S0 to S5, used for the A counter, are defined in Table 1. Bits S6
and S7 are reserved.
RF109
Synthesizer Loop Filter. A typical loop filter design is shown
below in Figure 3. The loop bandwidth is approximately 5 kHz
with a nominal phase margin of 45 degrees for a VCO sensitivity
of 60 MHz/V.
CHPO
pin 43
0.01µF
390
pF
1 0 kΩ
1 0 kΩ
VCOTUNE
330
pF
Figure 3. Typical Loop Filter
Power Management __________________________________
Independent power-up/power-down control of the transmit path,
receive path, and frequency synthesizer is provided by the
TXEN, RXEN and SYNTHEN controls, respectively. When all of
the functions are powered down, the current drain from the
voltage supply (Vcc) is at a minimum.
DATA MSB
CLK
STROBE
t1
t2
t3
t1 =Data setup time
t2 =Data hold time
t3 =Clock pulse-width
t4 =STROBE enable pulse-width
t5 =STROBE setup time to the rising edge of the last clock
t1 to t5 > 1µs each
Figure 4. Timing Diagram
LSB
t4
t5
100646A
Conexant
3
1/19/00
Conexant Proprietary
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