NJU8402M データシートの表示（PDF） - Japan Radio Corporation
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NJU8402M Datasheet PDF : 10 Pages
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NJU8402
(1-5) Control Register
The Control Register controls NJU8402 operation using the serial interface. The SCK terminal is the data
sift clock, the REQ terminal is data request signal, the DATA terminal is the serial data input. The control
data is loaded into the sift register at rising edge of SCK, then it is latched at the rising edge of REQ. The
least 8-bit data, which order is MSB first, is valid for control.
REQ
SCK
DATA
B7 B6 B5 B4 B3 B2 B1 B0
CONTROL PORT TIMING CHART
• Serial Data Format
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
∗
DIF1 DIF0 CLKR
0
0
0
1
∗
∗
∗
RST (∗: Don’t Care)
*1 Don't input commands except this table.
0
1
System Clock CLKR
256fs
384fs
Data Length
Format
DIF0
DIF1
16
18
I2S
LSB Justified
Reset
RST
Normal
Reset
*2 The level becomes 0 after initial setting.
Default
0
0
0
*2
-4-
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