AD9501JN(RevB) データシートの表示（PDF） - Analog Devices
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AD9501JN Datasheet PDF : 12 Pages
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AD9501
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 11
+VS
Positive Voltage Supply; Nominally 5 V.
2
LATCH
TTL/CMOS Register Control Line. Logic HIGH latches input data D0–D7. Register is transparent
for logic LOW.
3
TRIGGER
TTL/CMOS-Compatible Input. Rising edge triggers the internal ramp generator and begins
the delay cycle.
4
RESET
TTL/CMOS-Compatible Input. Logic HIGH resets the ramp voltage and OUTPUT.
5
DAC OUTPUT
Output Voltage of the Internal Digital-to-Analog Converter.
6
CEXT
Optional External Capacitor Connected to +VS. Used with RSET and 8.5 pF internal capacitor
to determine full-scale delay range (tDFS).
OBSOLETE 7
8
9, 20
10
12–19
RSET
OFFSET ADJUST
GROUND
OUTPUT
D0–D7
External Resistor to Ground. Used to determine full-scale delay range (tDFS).
Normally Connected to GROUND. Can be used to adjust minimum propagation delay (tPD);
see Theory of Operation section.
Circuit Ground Return.
TTL-Compatible Delayed Output Pulse.
TTL/CMOS-Compatible Inputs. Used to set the programmed delay of the AD9501 delayed
output. D0 is the LSB and D7 is the MSB.
+VS
D0–D7
LATCH
TRIGGER
RESET
+VS
+VS
+VS
+VS
DAC
OUTPUT
128⍀
INTERNAL
DAC
CEXT
OUTPUT
OFFSET
ADJUST
RSET
Figure 1. Equivalent Circuits
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9501 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
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