AD9501 データシートの表示（PDF） - Analog Devices

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AD9501

Digitally Programmable Delay Generator

Analog Devices 

AD9501

Analog Settling Time Measurement

This circuit, shown in Figure 9, functions in a manner similar to

the digital delay detector; for this application, too, the clock

must be repetitive. As in the delay detector, AD9501 #1 is used

to cancel the propagation delay of AD9501 #2, propagation

delay of the comparators, stray delays, etc. To accomplish this,

use the calibration procedure described earlier for the digital

delay generator.

The difference between the two circuits is in the detection

method. The register of the digital delay is replaced by a win-

dow comparator for the analog settling measurement.

Threshold voltages V1 and V2 are set for the desired tolerance

around the final value of the DUT output signal. As shown in

the lower portion of the diagram, the output of the detector is

high when the analog output signal of the converter is within the

limits set by V1 and V2.

Therefore, the settling time can be measured by starting the

delay of AD9501 #2 at its maximum setting and decrementing

it until the window comparator goes low. The difference

between the DAC codes applied to AD9501 #2 and AD9501

#1 is a measure of the settling time of the D/A converter being

tested.

Figure 9. Analog Settling Time Measurement

Layout Considerations

Although the inputs and output of the AD9501 are digital, the

delay is determined by analog circuits. This makes it critical to

use high speed analog circuit layout techniques to achieve rated

performance.

The ground plane should be on the component side of the

board and extend under the AD9501 to shield it from digital

switching signals. Most socket assemblies add significant

inter-lead capacitance, and should be avoided whenever pos-

sible. If sockets must be used, individual pin sockets such as

AMP part number 6330808-0 (closed knock-out end) or

6-330808-3 (open end) should be used.

Power supply decoupling is also critical for high speed design; a

0.1 µF capacitor should be connected as close as possible to

each supply pin.

REV. A

–11–

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