XE1203 データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

メーカー

XE1203

433MHz / 868MHz / 915MHz Low-power, integrated UHF transceiver

Unspecified 

Data Sheet

XE1203

4.1.5 Bit synchronizer

The output of the demodulator has glitches and jitters. The bit synchronizer transforms the data output of the

demodulator into a glitch-free bit stream DATA and generates a synchronized clock DCLK to be used for sampling

the DATA output (see below).

DATA

(NRZ)

DCLK

Figure 2. Bit synchronizer timing diagram.

To ensure proper behaviour of the bit synchronizer, three conditions have to be satisfied: A preamble of 24 bits is

required for the synchronization; this preamble must be a sequence of “0” and “1” sent alternatively, during

transmission of data, the bit stream must have at least one transition from “0” to “1” or from “1” to “0” every 8 bits.

The accuracy of the bit rate must be better than ± 5 %. The bit synchronizer is on when RTParam_Bsync is high.

FSParam_BR defines the bit rate in the following way.

Bit rate =

152.34e3

int(FSParam_BR(6

:

0))

+

1

,

where int(x) is the integer value of the unsigned binary representation of x.

If the Konnex standard is used then the bit rate is fixed and equal to 32.77 Kbps. The register FSParam_OSR

(address “00101” ) has to be set to “00011110” , the register FSParam_BR(6:0) has to be set to “000X0000” and

the bit FSPARAM_Change_Osr has to be set to ‘1’.^

10

D0308-214

Share Link: