XE1202A データシートの表示（PDF） - Semtech Corporation

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XE1202A

433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver

Semtech Corporation 

XE1202A TrueRF™

4 Description

The XE1202A TrueRF™ is a direct conversion (Zero-IF) half-duplex data transceiver. It includes a receiver, a

transmitter, a frequency synthesizer and some service blocks. The circuit operates in the 3 ISM frequency bands

(433 MHz, 868 MHz, 915 MHz) and uses 2-level FSK modulation/demodulation to provide a complete transmission

link.

In a typical application, the XE1202A TrueRF™ is programmed by a microcontroller via the 3-wire serial bus, SI,

SO, SCK to write to and read from the configuration registers.

The circuit consists of 5 main functional blocks:

The Receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is

composed of a low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters,

demodulator and the bit synchronizer. The bit synchronizer transforms the data output of the demodulator into a

glitch-free bit stream DATAOUT and generates a synchronized clock, DCLK, which can be used to sample

DATAOUT without requiring external signal processing. In addition, the receiver includes a Received Signal

Strength Indicator (RSSI) function, a Frequency Error Indicator (FEI) function that provides an indication of local

oscillator frequency error, and pattern recognition function to detect programmable reference words in the received

bit stream. The bandwidth of the base-band filters, the frequency deviation of the expected incoming FSK signal as

well as the bit rate of the received data are all programmable.

The Transmitter performs the modulation of the carrier by an input bit stream and the transmission of the

modulated signal. Carrier modulation is achieved directly through the frequency synthesizer via a Sigma-Delta

modulator. The frequency deviation and bit rate of the modulated carrier are programmable. An on-chip power

amplifier then amplifies the signal. The output power can be programmed to one of 4 possible settings.

The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the

continuous phase FSK (CPFSK) modulated signal for the transmitter section. The core of the synthesizer is

implemented with a PLL structure. The frequency is programmable with a step size of 500 Hz in the 3 ISM

frequency bands at 433, 868 and 915 MHz. This frequency synthesizer includes a crystal oscillator which provides

the reference for the PLL. This reference frequency can be divided by 4, 8, 16 or 32 and available as CLKOUT to

provide a clock signal for an external processor.

The Digital Interface provides internal control signals for the whole circuit according to the configuration register

settings.

The Service Block provides the internal voltage and current sources and provides all the necessary functions for

the circuit to work properly.

4.1 Detailed description

4.1.1 Receiver

The outputs of the receiver are the two signals DATAOUT and DCLK. When “RTParam_Bits” is set to “1” (see the

Configuration register section below), the bit synchronizer is enabled, and the two output signals are the output

NRZ demodulated data and the sampling clock, respectively. The function of the bit synchronizer is to remove the

glitches from DATAOUT and to provide the output clock DCLK to sample the data. The value of DATAOUT is valid

at the rising edge of DCLK.

To ensure correct operation of the bit synchronizer, the following three conditions must be satisfied:

the received data must start with a preamble of 24 bits for synchronization; this preamble must be a sequence of

alternating “0” and “1”,

the received data must have at least one transition from “0” to “1” or from “1” to “0” every 8 bits,

the accuracy of the bit rate must be within ± 5 % of that programmed (assuming the reference Xtal oscillator is 39

MHz).

© Semtech 2006

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