XRT72L71 データシートの表示（PDF） - Exar Corporation

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XRT72L71

DS3 ATM UNI/CLEAR CHANNEL FRAMER

Exar Corporation 

XRT72L71 DS3 ATM UNI/CLEAR CHANNEL FRAMER IC

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REV. 1.1.0

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................ 1

APPLICATIONS .............................................................................................................................................. 1

FEATURES .................................................................................................................................................... 1

Figure 1. XRT72L71 Simplified Block Diagram with System Interfaces ............................................................ 1

Figure 2. Block Diagram of the XRT72L71 DS3 UNI ........................................................................................ 2

Figure 3. Pin Out of the XRT72L71 DS3 ATM UNI ........................................................................................... 3

ORDERING INFORMATION ............................................................................................... 3

TABLE OF CONTENTS .................................................................................................................................... I

PIN DESCRIPTIONS (see Figure 3) ............................................................................................................... 4

PIN DESCRIPTION ........................................................................................................... 4

ABSOLUTE MAXIMUM RATINGS ................................................................................... 23

DC ELECTRICAL CHARACTERISTICS .......................................................................... 23

AC ELECTRICAL CHARACTERISTICS .......................................................................... 23

TIMING DIAGRAMS ...................................................................................................... 28

Figure 4. XRT72L71 Transmit UTOPIA Interface Block Timing ...................................................................... 28

Figure 5. GFC Nibble-Field Serial Input Interface (at Transmit Cell Processor) Timing ................................. 28

Figure 6. Transmit PLCP Processor—POH Byte Serial Input Port Interface Timing ...................................... 29

Figure 7. Transmit DS3 Framer—OH Bit Serial Input Port Interface Timing ................................................... 29

Figure 8. Transmit DS3 Framer Line Interface Output Timing (TxPOS and TxNEG are updated on the rising

edge of TxLineClk) ........................................................................................................................ 30

Figure 9. Transmit DS3 Framer Line Interface Output Timing (TxPOS and TxNEG are updated on the falling

edge of TxLineClk) ........................................................................................................................ 30

Figure 10. Receive DS3 Framer—OH Bit Serial Output Port Interface Timing ............................................... 31

Figure 11. Receive DS3 Framer Line Interface Input Signal Timing (RxPOS and RxNEG are sampled on rising

edge of RxLineClk) ....................................................................................................................... 31

Figure 12. Receive DS3 Framer Line Interface Input Signal Timing (RxPOS and RxNEG are sampled on the

falling edge of RxLineClk) ............................................................................................................. 32

Figure 13. Receive PLCP Processor—POH Byte Serial Output Port Interface Timing .................................. 32

Figure 14. GFC Nibble-Field Serial Output Port Timing (Receive Cell Processor) ......................................... 33

Figure 15. Receive UTOPIA Interface Block Timing ....................................................................................... 33

Figure 16. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ........................ 34

Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ........................ 34

Figure 18. Microprocessor Interface Timing—Motorola Type Processors (Read Operations) Non-Burst Mode .

35

Figure 19. Microprocessor Interface Timing—Motorola Type Processor (Write Operations) Non-Burst Mode ...

35

Figure 20. Microprocessor Interface Timing - Reset Pulse Width ................................................................... 35

FUNCTIONAL DESCRIPTION ......................................................................................... 36

THE ATM UNI MODE OF OPERATION ......................................................................... 36

The Receive Section ..................................................................................................... 36

The Transmit Section .................................................................................................... 37

Clear-channel-framing Mode of operation .................................................................. 38

THE RECEIVE SECTION.......................................................................................................................................38

THE TRANSMIT SECTION ....................................................................................................................................38

The Microprocessor Interface Section ........................................................................ 39

Performance Monitor Section ...................................................................................... 39

Test and Diagnostic Section ........................................................................................ 39

FOR ATM UNI APPLICATIONS .............................................................................................................................39

FOR CLEAR-CHANNEL FRAMING APPLICATIONS............................................................................................39

Line Interface Drive and Scan Section ........................................................................ 40

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