XRT91L31IQ-F データシートの表示（PDF） - Exar Corporation

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XRT91L31IQ-F

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

Exar Corporation 

REV. 1.0.2

RECEIVER SECTION

PIN DESCRIPTION

NAME

LEVEL

RXDO0

RXDO1

RXDO2

RXDO3

RXDO4

RXDO5

RXDO6

RXDO7

LVTTL,

LVCMOS

RXIP

RXIN

Diff LVPECL

TYPE

O

I

XRXCLKIP

Diff LVPECL

I

XRXCLKIN

RXPCLKO

LVTTL,

O

LVCMOS

CDRAUX-

LVTTL,

I

REFCLK

LVCMOS

OOF

LVTTL,

I

LVCMOS

XRT91L31

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

PIN

DESCRIPTION

19 Receive Parallel Data Output

20 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)

22 8-bit parallel receive data output is updated simultaneously on

23

the falling edge of the RXPCLKO output. The 8-bit parallel

24

interface is de-multiplexed from the receive serial data input

MSB first (RXDO[7]). The XRT91L31 will output the data on the

25

falling edge of RXPCLKO clock.

26

27

13 Receive Serial Data Input

14 The differential receive serial data stream of 622.08 Mbps

STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to

these input pins. These pins have internal LVPECL common-

mode biasing circuit. External 100R termination is required

between RXIP/N pins.

8

External Recovered Receive Clock Input

9

The differential receive serial data stream of 622.08 Mbps

STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on

the rising edge of this externally recovered differential clock

coming from the optical module. It is used when the internal

CDR unit is disabled and bypassed by the CDRDIS pin.

These pins have internal LVPECL common-mode biasing cir-

cuit. External 100R termination is required between XRX-

CLKIP/N pins.

NOTE: In the event that XRXCLKIP/N differential input pins are

unused, XRXCLKIP should be tied to VCC with a 1k

Ohm pull-up and XRXCLKIN should be tied to Ground

with a 1k Ohm pull-down.

29 Receive Parallel Clock Output (77.76 MHz or 19.44 MHz)

77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)

clock output reference for the 8-bit parallel receive data output

RXDO[7:0]. The parallel received data output bus will be

updated on the falling edge of this clock.

32 Clock and Data Recovery Auxillary Reference Clock

77.76 MHz ± 200 ppm auxillary reference clock for the CDR.

NOTE: In the event that CDRAUXREFCLK LVTTL input pin is

unused, CDRAUXREFCLK should be tied to ground.

11 Out of Frame Input Indicator

This level sensitive input pin is used to initiate frame detection

and byte alignment recovery when OOF is declared by the

downstream device. When this pin is held High, FRAME-

PULSE will pulse for a single RXPCLKO period upon the detec-

tion of every third frame alignment A2 byte in the incoming

SONET/SDH Frame.

"Low" = Normal Operation

"High" = OOF Indication initiating frame detection and byte

boundary recovery and activating FRAMEPULSE

11

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