XRT91L34 データシートの表示（PDF） - Exar Corporation
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XRT91L34 Datasheet PDF : 38 Pages
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XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
TABLE OF CONTENTS
REV. 1.0.1
GENERAL DESCRIPTION .................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L34 ...................................................................................................................................... 1
APPLICATIONS ...........................................................................................................................................2
FEATURES ......................................................................................................................................................2
FIGURE 2. 128 LQFP PIN OUT OF THE XRT91L34 (TOP VIEW)........................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3
TABLE OF CONTENTS .......................................................................................................... IV
PIN DESCRIPTIONS ..........................................................................................................6
HARDWARE CONTROL ....................................................................................................................................6
RECEIVER SECTION........................................................................................................................................9
POWER AND GROUND ..................................................................................................................................10
SERIAL MICROPROCESSOR INTERFACE ......................................................................................................11
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12
1.2 STS-12/STM-4 AND STS-3/STM-1 AND STS-1/STM-0 MODE OF OPERATION ......................................... 12
TABLE 1: CHANNEL DATA RATE SELECTION .................................................................................................................................... 12
1.3 REFERENCE CLOCK INPUT ......................................................................................................................... 13
TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS)............................ 13
FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS............................................................................................................................ 13
2.0 RECEIVE SECTION .............................................................................................................................14
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM....................................... 14
FIGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION ..................................... 15
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 16
2.2.1 INTERNAL CLOCK AND DATA RECOVERY DISABLE ........................................................................................... 16
2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16
2.4 INTERNAL DIGITAL LOSS OF SIGNAL AND EXTERNAL SIGNAL DETECTION ...................................... 17
FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT ........................................................................................................................ 17
TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING........................................................................................................... 17
2.5 MULTICHANNEL RECOVERED OUTPUT INTERFACE ............................................................................... 18
FIGURE 8. MULTICHANNEL RECOVERED OUTPUT INTERFACE BLOCK................................................................................................ 18
2.6 DIFFERENTIAL RECOVERED DATA OUTPUT TIMING ............................................................................... 19
FIGURE 9. DIFFERENTIAL RECOVERED OUTPUT TIMING ................................................................................................................... 19
TABLE 5: RECOVERED DATA OUTPUT TIMING (STS-12/STM-4 OPERATION).................................................................................... 19
TABLE 6: RECOVERED DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)...................................................................................... 19
TABLE 7: RECOVERED DATA OUTPUT TIMING (STS-1/STM-0 OPERATION)...................................................................................... 19
3.0 JITTER PERFORMANCE ....................................................................................................................20
3.1 SONET JITTER REQUIREMENTS ................................................................................................................. 20
3.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 20
FIGURE 10. GR-253/G.783 JITTER TOLERANCE MASK ................................................................................................................... 20
FIGURE 11. XRT91L34 MEASURED JITTER TOLERANCE AT 51.84 MBPS STS-1/STM-0 .................................................................. 20
FIGURE 12. XRT91L34 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3/STM-1 ................................................................ 21
FIGURE 13. XRT91L34 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4 .............................................................. 21
3.1.2 RX JITTER TRANSFER .............................................................................................................................................. 22
FIGURE 14. XRT91L34 MEASURED JITTER TRANSFER AT 51.84 MBPS STS-1/STM-0 .................................................................... 22
FIGURE 15. XRT91L34 MEASURED JITTER TRANSFER AT 155.52 MBPS STS-3/STM-1 .................................................................. 22
FIGURE 16. XRT91L34 MEASURED JITTER TRANSFER AT 622.08 MBPS STS-12/STM-4 ................................................................ 23
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................24
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 24
4.1 SERIAL TIMING INFORMATION .................................................................................................................... 24
FIGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 24
4.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 25
4.2.1 R/W (SCLK1) ............................................................................................................................................................... 25
4.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 25
4.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 25
4.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 25
4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 25
IV
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