XRT91L80 データシートの表示（PDF） - Exar Corporation

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XRT91L80

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

XRT91L80

PRELIMINARY

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

TABLE OF CONTENTS

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REV. P1.1.0

GENERAL DESCRIPTION .................................................................................................1

APPLICATIONS ...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF XRT91L80 ...................................................................................................................................... 1

FEATURES ......................................................................................................................................................2

PRODUCT ORDERING INFORMATION ..................................................................................................2

FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW).......................................................................................................... 3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS ..........................................................................................................4

SERIAL MICROPROCESSOR INTERFACE............................................................................................................4

HARDWARE COMMON CONTROL ......................................................................................................................5

TRANSMITTER SECTION ..................................................................................................................................6

RECEIVER SECTION.........................................................................................................................................9

POWER AND GROUND ..................................................................................................................................10

NO CONNECTS.............................................................................................................................................11

JTAG ..........................................................................................................................................................12

1.0 FUNCTIONAL DESCRIPTION .............................................................................................................13

1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 13

1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 13

TABLE 1: REFERENCE FREQUENCY OPTIONS (NON-FEC AND FEC MODE) ...................................................................................... 13

1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 13

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 13

2.0 RECEIVE SECTION .............................................................................................................................14

2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14

FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 14

TABLE 2: DIFFERENTIAL CML INPUT SWING PARAMETERS .............................................................................................................. 14

2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15

TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 15

2.3 EXTERNAL SIGNAL DETECTION ................................................................................................................. 15

TABLE 4: LOSD DECLARATION POLARITY SETTING ......................................................................................................................... 16

2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 16

FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 16

2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 16

FIGURE 6. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 16

2.6 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 17

FIGURE 7. LVDS EXTERNAL BIASING RESISTORS............................................................................................................................. 17

2.7 PARALLEL RECEIVE DATA OUTPUT MUTE UPON LOSD ........................................................................ 17

2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE ......................................................................................... 17

2.9 RECEIVE PARALLEL DATA OUTPUT TIMING ............................................................................................ 17

FIGURE 8. RECEIVE PARALLEL OUTPUT TIMING .............................................................................................................................. 17

TABLE 5: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS ........................................................................... 17

3.0 TRANSMIT SECTION ..........................................................................................................................18

3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 18

FIGURE 9. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................... 18

3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 19

FIGURE 10. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 19

TABLE 6: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION............................................................................... 19

TABLE 7: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION ........................................................................................... 19

3.3 TRANSMIT FIFO ............................................................................................................................................. 19

FIGURE 11. TRANSMIT FIFO AND SYSTEM INTERFACE .................................................................................................................... 20

3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 20

3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 20

FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 20

3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 21

TABLE 8: CLOCK MULTIPLIER UNIT PERFORMANCE ......................................................................................................................... 21

3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 21

TABLE 9: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS .............................................................................................. 22

FIGURE 13. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO .......................................................................................... 22

3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 23

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