XRT91L82 データシートの表示（PDF） - Exar Corporation

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XRT91L82

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

XRT91L82

REV. P1.0.5

PRELIMINARY

xr

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................1

APPLICATIONS ...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF XRT91L82 ...................................................................................................................................... 1

FEATURES ......................................................................................................................................................2

PRODUCT ORDERING INFORMATION ..................................................................................................2

FIGURE 2. 196 BGA PINOUT OF THE XRT91L82 (TOP VIEW).......................................................................................................... 3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS ..........................................................................................................4

COMMON CONTROL .....................................................................................................................................4

TRANSMITTER SECTION ..................................................................................................................................8

RECEIVER SECTION.......................................................................................................................................11

SERIAL MICROPROCESSOR INTERFACE .............................................................................................14

...................................................................................................................................................................14

JTAG ..........................................................................................................................................................15

1.0 FUNCTIONAL DESCRIPTION .............................................................................................................16

1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 16

1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 16

TABLE 1: REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE)...................................................................................... 16

1.3 ALTERNATE CLOCK INPUT REFERENCE (HOST MODE ONLY) .............................................................. 16

TABLE 2: ALTERNATE REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE) ................................................................... 17

1.4 DATA LATENCY ............................................................................................................................................. 17

TABLE 3: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 17

1.5 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 17

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 17

1.6 PRBS PATTERN GENERATOR AND ANALYZER ....................................................................................... 17

2.0 RECEIVE SECTION .............................................................................................................................18

2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 18

FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 18

TABLE 4: DIFFERENTIAL CML INPUT SWING PARAMETERS .............................................................................................................. 18

2.2 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19

FIGURE 5. EXTERNAL LOOP FILTER ................................................................................................................................................ 19

2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 19

TABLE 5: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 20

2.4 EXTERNAL SIGNAL DETECTION ................................................................................................................. 20

TABLE 6: LOSD DECLARATION POLARITY SETTING ......................................................................................................................... 20

2.5 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 21

FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 21

2.6 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21

FIGURE 7. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 21

2.7 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 22

FIGURE 8. LVDS EXTERNAL BIASING RESISTORS............................................................................................................................. 22

2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE/MUTE UPON LOSD ........................................................ 22

2.9 PARALLEL RECEIVE CLOCK OUTPUT DISABLE ...................................................................................... 22

2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22

FIGURE 9. RECEIVE PARALLEL OUTPUT TIMING .............................................................................................................................. 22

TABLE 7: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS ........................................................................... 22

3.0 TRANSMIT SECTION ..........................................................................................................................23

3.1 TRANSMIT PARALLEL INTERFACE ............................................................................................................ 23

FIGURE 10. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 23

3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 24

FIGURE 11. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 24

TABLE 8: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION............................................................................... 24

TABLE 9: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION ........................................................................................... 24

3.3 TRANSMIT FIFO ............................................................................................................................................. 24

FIGURE 12. TRANSMIT FIFO AND SYSTEM INTERFACE .................................................................................................................... 25

3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 25

3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25

FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 25

I

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