XRT91L82 データシートの表示（PDF） - Exar Corporation
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XRT91L82 Datasheet PDF : 59 Pages
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PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
REV. P1.0.5
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
TABLE 10: CLOCK MULTIPLIER UNIT PERFORMANCE ....................................................................................................................... 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 26
TABLE 11: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS ............................................................................................ 27
FIGURE 14. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO (HOST MODE ONLY) .......................................................... 27
3.8 EXTERNAL LOOP FILTER (HOST MODE ONLY) ........................................................................................ 28
FIGURE 15. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER .................................................................................................. 28
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
FIGURE 16. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 28
TABLE 12: DIFFERENTIAL CML OUTPUT SWING PARAMETERS......................................................................................................... 28
FIGURE 17. CML DIFFERENTIAL VOLTAGE SWING........................................................................................................................... 29
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 30
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 30
FIGURE 18. SERIAL REMOTE LOOPBACK......................................................................................................................................... 30
4.2 PARALLEL REMOTE LOOPBACK (HOST MODE ONLY) ........................................................................... 30
FIGURE 19. PARALLEL REMOTE LOOPBACK .................................................................................................................................... 30
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 31
FIGURE 20. DIGITAL LOOPBACK...................................................................................................................................................... 31
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 32
4.4.1 JITTER TOLERANCE: ................................................................................................................................................ 32
FIGURE 21. JITTER TOLERANCE MASK............................................................................................................................................ 32
FIGURE 22. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16 ............................ 33
FIGURE 23. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE ..................................... 33
4.4.2 JITTER TRANSFER .................................................................................................................................................... 33
FIGURE 24. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16 .............................. 33
FIGURE 25. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE ....................................... 33
4.4.3 JITTER GENERATION................................................................................................................................................ 34
FIGURE 26. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS .............................. 34
FIGURE 27. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.666 GBPS .............................. 34
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ......................................................................... 35
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 35
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 35
FIGURE 29. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 35
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 36
5.2.1 R/W (SCLK1)............................................................................................................................................................... 36
5.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 36
5.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 36
5.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 36
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 36
6.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 37
TABLE 13: MICROPROCESSOR REGISTER MAP................................................................................................................................ 37
TABLE 14: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 38
TABLE 15: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 39
TABLE 16: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 40
TABLE 17: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 41
TABLE 18: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 42
TABLE 19: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ................................................................................................. 43
TABLE 20: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION ................................................................................................. 45
TABLE 21: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION ................................................................................................. 46
TABLE 22: MICROPROCESSOR REGISTER 0X3CH BIT DESCRIPTION................................................................................................. 48
TABLE 23: MICROPROCESSOR REGISTER 0X3DH BIT DESCRIPTION................................................................................................. 49
TABLE 24: MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION ................................................................................................. 49
7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 50
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 50
ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS ............................................................. 50
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 50
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS .......................................................... 51
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS............................................................... 51
LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ........................................................... 52
ORDERING INFORMATION .................................................................................................................. 53
196 SHRINK THIN BALL GRID ARRAY .............................................................................................. 53
(15.0 MM X 15.0 MM, STBGA).......................................................................................................... 53
II
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