SN74LS139ML1 データシートの表示（PDF） - ON Semiconductor

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SN74LS139ML1

Dual 1-of-4 Decoder/Demultiplexer

ON Semiconductor 

SN74LS139

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Eb A0b A1b O0b O1b O2b O3b

16 15 14 13 12 11 10 9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1 2 3 4 56 78

Ea A0a A1a O0a O1a O2a O3a GND

PIN NAMES

A0, A1

E

O0 – O3

Address Inputs

Enable (Active LOW) Input

Active LOW Outputs

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL

1

23

15 14 13

E

A0 A1

DECODER a

O0 O1 O2 O3

E

A0 A1

DECODER b

O0 O1 O2 O3

4567

12 11 10 9

VCC = PIN 16

GND = PIN 8

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