SMP9212S データシートの表示（PDF） - Summit Microelectronics
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SMP9212S Datasheet PDF : 13 Pages
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SMP9210, SMP9211, SMP9212
Preliminary
Symbol
Parameter
Conditions
fSCL
tLOW
t
HIGH
tBUF
tSU:STA
tHD:STA
tSU:STO
tAA
tDH
tR
tF
tSU:DAT
tHD:DAT
TI
SCL clock frequency
Clock low period
Clock high period
Bus free time (1)
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output (1)
Data Out hold time (1)
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time (1)
Data In hold time (1)
Noise filter SCL and SDA (1)
Before new transmission
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA change
Noise suppression
tWR
Write cycle time
Note (1) These values are guaranteed by design.
Table 1. Data/Clock Timing
Min.
0
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
250
0
Max. Units
100
kHz
µs
µs
µs
µs
µs
µs
3.5
µs
µs
1000
ns
300
ns
ns
ns
100
ns
5
ms
2048 Table01 2.0
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
Command
Function
1 0 0 1 x x D9 D8 Write DAC1
Write 10-Bit value to DAC1
1 0 1 0 x x D9 D8 Write DAC2
Write 10-Bit value to DAC2
1 0 1 1 x x D9 D8 Write both DACs Write 10-Bit value to both DACs
1 1 0 1 1 1 1 0 3F DAC2
Set DAC2 to full scale (VREFH)
1 1 0 1 1 1 0 1 3F DAC1
Set DAC1 to full scale (VREFH)
1
1
0
1
1
1
1
1 3F both DACs Set both DACs to full scale (VREFH)
1 1 1 0 1 1 1 0 Zero DAC2
Set DAC2 to zero scale (VREFL)
1 1 1 0 1 1 0 1 Zero DAC1
Set DAC1 to zero scale (VREFL)
1
1
10
1
1
1
1 Zero both DACs Set both DACs to zero scale (VREFL)
1 1 1 1 x x 1 0 Recall DAC2
Recall E2 to DAC2
1 1 1 1 x x 0 1 Recall DAC1
Recall E2 to DAC1
11
1
1x
x
1
1 Recall both DACs Recall E2 to both DACs
1 0 0 0 x x 1 0 PD DAC2
Power down DAC2 (VOUT to GND)
1 0 0 0 x x 0 1 PD DAC1
Power down DAC1 (VOUT to GND)
10
0
0
x
x
1
1 PD both DACs Power down both DACs (VOUT to GND)
2048 Table02 3.0
Table 2. Command Structure
8
2048 3.3 10/03/01
SUMMIT MICROELECTRONICS, Inc.
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