SMP9212S データシートの表示（PDF） - Summit Microelectronics
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SMP9212S Datasheet PDF : 13 Pages
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SMP9210, SMP9211, SMP9212
Preliminary
The command structure is illustrated in Table 2. Of
special note is the ability to write individually to either of
the two DACs, or write to them both. The first three
commands are three bytes in length and can either be
volatile or nonvolatile.
edge followed by the Master writing the last eight bits. If
no Stop is generated after the device Acknowledge the
Write is only to the register. If the device Acknowledge
is followed by a Stop the data is written to both the DAC
register and to the nonvolatile register.
ACK and NACK
A device that is receiving data will respond with an
Acknowledge by pulling the SDA line low (ACK) after each
byte is transmitted. The transmitting device will recog-
nize this and continue to transmit. When the Master has
received the data it expects it will hold the SDA line high
(NACK) and the transmitting device will end transmis-
sion.
Sequence
The sequence is to issue a Start, followed by the device
type and bus address with the Read/Write bit set to zero.
The device will respond with an Acknowledge and the
Master will then issue the command and follow-on data.
In Figure 3 the Write is to DAC1 where the command =
1001BIN; D9 and D8 are the MSBs of the DAC value being
written. The device will then respond with an Acknowl-
Reading the Device
Reading the DACs requires setting the R/W bit to one.
Then the host supplies clocks and the device will output
data as shown in Figure 4. PD is the Power Down mode
indicator: 1 = power down, 0= DAC active. Both DACs
provide their data for a single Read operation.
Special Configurations
The SMP9210 can be configured by the end user or by
Summit prior to shipment (see page 10). Reading the
configuration register can also be performed if it has not
already been locked. See Figure 5. There is one
configuration register and it is accessed through the serial
interface using 1001BIN as the device type address,
consequently the DAC address should never be set to
1001BIN. The register is shown in Table 3.
Master
SDA
Slave
Nonvolatile Write Only
S
T
R/
O
W
P
0
1
0
1
A
2
A
1
A
0
0
1
0
0
1
x
x
D
9
D
8
DDDDDDDD
76543210
A
A
A
C
C
C
K
K
K
2048 Fig03
Figure 3. DAC1 Write Operation (see Table 2)
Master
SDA
Slave
Data from Master
DAC #1
R/
W
Data to Master
A
C
K
NS
AT
CO
KP
0
1
0
1
AA
21
A
0
1
1
0
0
1
1
PDD
D9 8
DDDDDD DD
765432 10
A
C
K (1 0 1 0)
2048 Fig04
DAC #2
Figure 4. Read DAC1 (See DAC2 Differentiator & Table 2)
SUMMIT MICROELECTRONICS, Inc.
2048 3.3 10/03/01
9
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