E-L6452 データシートの表示（PDF） - STMicroelectronics
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E-L6452 Datasheet PDF : 22 Pages
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Pin description
L6452
Table 1. Pin function - continued
Pin #
Name
Function
3, 7, 10, 13,
17, 20, 23,
26
Vc
Outputs Power Supply
4, 15, 27,
51, 79, 92
29
GND
LatchClear
logic and power ground
A high level resets all bit in the latch
A high level enables the internal current sources and disables all
30
NcEn
DMOS outputs. To be active, the internal current sources must have
their corresponding bit set in the 16 bit latch and LongPulse must be
set to low level. This function is called Nozzle Check Enable.
31
LatchData
A rising edge latches the 16 bit stored in the shift register in the 16 bit
latch
32
SDI
Serial data input of the shift register
33
SDC
The data bit presented to the SDI pin is stored into the register on the
rising edge of this pin
34
LongPulse
A low level activates all outputs having their corresponding bit in the
16 bit latch set (this pin has an internal pull-up resistor)
35
ShortPulse
A low level activates all outputs having their corresponding bit in the
16 bit latch reset (this pin has an internal pull-up resistor)
36
Reset
A low level disables all functions and clears all registers
37
ConvStart A high level enables the A/D to start the new conversion
38
ADCK
A/D clock signal; the ADDATA signal are valid on the falling edge of
this pin
If NcEn is high this output provides a high level when the open load is
39
NCOut
detected on the output. If NcEn is low this output provides a high level
when a short circuit is detected on HSA/B output
40
CH0buf
Analog output signal (CH0 buffered)
41
ADDATA
A/D serial data output
42
AnalogGND Analog ground connection
43
ADCGND Ground of internal ADC
44, 90
45
Va
Power supply
Vref
Reference voltage generator
46 to 50
CH5..CH1 A/D input signals
52 to 64
HSB1..HSB13 Head selector address output channel B
65
66 to 78
Vr
Head Select Power Supply
HSA13..HSA1 Head selector address output channel A
Enable Internal Counter:
80
EnlC
A high level enables the counter and the internal decoder will activate
of the HSx outputs according to the counter’s outputs. Signal S0
becomes ClkC and S1 becomes ResC
6/22
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