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74V2G00CTR データシートの表示(PDF) - STMicroelectronics

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74V2G00CTR
ST-Microelectronics
STMicroelectronics ST-Microelectronics
74V2G00CTR Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
74V2G00
s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 1µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The V2G00 is an advanced high-speed CMOS
SINGLE 2-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS tecnology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
DUAL 2-INPUT NAND GATE
PRELIMINARY DATA
SOT23-8L
SOT323-8L
ORDER CODES
PACKAGE
SOT23-8L
SOT323-8L
T&R
74V2G00STR
74V2G00CTR
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 2001
1/9
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

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