CY8C24693 データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY8C24693 Datasheet PDF : 65 Pages
| |||
CY8C24X93
32-pin QFN (28 GPIOs) [6]
Table 3. Pin Definitions – CY8C24193 [7]
Pin
No.
Type
Digital Analog
Name
Description
1
IOH
I
P0[1]
2
I/O
I
P2[7]
3
I/O
I
P2[5] Crystal output (XOut)
4
I/O
I
P2[3] Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P3[3]
7
I/O
8
IOHR
9
IOHR
I
P3[1]
I
P1[7] I2C SCL, SPI SS
I
P1[5] I2C SDA, SPI MISO
10 IOHR
11 IOHR
I
P1[3] SPI CLK.
I
P1[1] ISSP CLK[8], I2C SCL, SPI MOSI.
12
Power
13 IOHR
I
VSS
P1[0]
Ground connection.
ISSP DATA[8], I2C SDA,
SPI CLK[9]
14 IOHR
I
P1[2]
15 IOHR
I
P1[4] Optional external clock input
(EXTCLK)
16 IOHR
I
P1[6]
17
Input
XRES Active high external reset with
internal pull-down
18
I/O
I
P3[0]
Figure 2. CY8C24193
AI , P0[1] 1
AI , P2[7] 2
AI, XOut, P2[5] 3
AI , XIn, P2[3] 4
AI , P2[1] 5
AI , P3[3] 6
AI , P3[1] 7
AI , I2 C SCL, SPI SS, P1[7] 8
24
23
22
QFN 21
(Top View) 20
19
18
17
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
28
Power
29
IOH
I
VDD Supply voltage
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
32
Power
CP
Power
VSS Ground connection
VSS
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
6. 28 GPIOs.
7.
The center pad (CP) on the QFN
it must be electrically floated and
package must be
not connected to
connected to ground
any other signal.
(VSS)
for
best
mechanical,
thermal,
and
electrical
performance.
If
not
connected
to
ground,
8. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
9. Alternate SPI clock.
Document Number: 001-86894 Rev. *B
Page 11 of 65
Share Link: 