74ALVT16260 データシートの表示（PDF） - NXP Semiconductors.

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74ALVT16260

12-bit to 24-bit multiplexed D-type latches; 3-state

NXP Semiconductors. 

Philips Semiconductors

74ALVT16260

12-bit to 24-bit multiplexed D-type latches; 3-state

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6;

Tamb = −40 °C to +85 °C

Symbol Parameter

Conditions

VCC = 3.3 V ± 0.3 V

tPLH

LOW-to-HIGH propagation delay

An to xBn; xBn to An

see Figure 3

LExB to An; LEAxB to xBn

SEL(1Bn) to An

SEL(2Bn) to An

tPHL

HIGH-to-LOW propagation delay

An to xBn; xBn to An

see Figure 3

LExB to An; LEAxB to xBn

SEL(1Bn) to An

SEL(2Bn) to An

tPZH

output enable time to HIGH-state

see Figure 4

OEA to An; OE1B to 1Bn; OE2B to 2Bn

tPZL

output enable time to LOW-state

see Figure 4

OEA to An; OE1B to 1Bn; OE2B to 2Bn

tPHZ

output disable time from HIGH-state

see Figure 4

OEA to An; OE1B to 1Bn; OE2B to 2Bn

tPLZ

output disable time from LOW-state

see Figure 4

OEA to An; OE1B to 1Bn; OE2B to 2Bn

tsu

setup time

An to LEAxB; xBn to LExB

see Figure 5

th

hold time

LEAxB to An; LExB to xBn

see Figure 5

tW

pulse width

LExB HIGH; LEAxB HIGH

see Figure 5

Min Typ Max Unit

0.7 2.2 3.6 ns

1.0 2.4 4.1 ns

1.0 2.2 3.4 ns

0.9 2.3 3.8 ns

0.7 2.0 3.4 ns

1.1 2.3 3.9 ns

1.0 2.0 3.3 ns

1.6 2.1 3.4 ns

1.1 2.7 4.1 ns

1.1 2.1 3.2 ns

2.4 3.4 4.8 ns

2.0 3.0 4.0 ns

1 - - ns

1 - - ns

3.3 - - ns

74ALVT16260_3

Product data sheet

Rev. 03 — 20 March 2006

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

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