74LVCU04ADB データシートの表示（PDF） - NXP Semiconductors.

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74LVCU04ADB

Hex unbuffered inverter

NXP Semiconductors. 

NXP Semiconductors

4. Functional diagram

74LVCU04A

Hex unbuffered inverter

1 1A

3 2A

5 3A

9 4A

11 5A

13 6A

1Y 2

2Y 4

3Y 6

4Y 8

5Y 10

6Y 12

mna926

Fig 1. Logic symbol

1

1

2

1

3

4

1

5

6

1

9

8

1

11

10

1

13

12

mna925

Fig 2. IEC logic symbol

5. Pinning information

5.1 Pinning

100 Ω

nA

VCC VCC

nY

mna927

Fig 3. Schematic diagram for one

inverter

1A 1

1Y 2

2A 3

2Y 4

3A 5

3Y 6

GND 7

14 VCC

13 6A

12 6Y

04

11 5A

10 5Y

9 4A

8 4Y

001aad062

Fig 4. Pin configuration for SO14 and (T)SSOP14

terminal 1

index area

1Y 2

2A 3

2Y 4

3A 5

3Y 6

04

GND(1)

13 6A

12 6Y

11 5A

10 5Y

9 4A

001aad063

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration for DHVQFN14

74LVCU04A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 8 — 18 December 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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