TDA7503 データシートの表示（PDF） - STMicroelectronics
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TDA7503 Datasheet PDF : 30 Pages
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TDA7503
PIN DESCRIPTION (continued)
N.
Name
Type
Reset
Status
42 SRA9/DRA5
O
High
43 DSP1_GPIO1 I/O
–
44 DSP0_GPIO1 I/O
–
45 SRA8/DRA4
O
High
46 SRA13/RAS
O
High
47
VSS6
GND
–
48
VDD6
PWR
–
49
DWR
O
High
50
ALE/CAS
O
High
51 SRA12/DRA8 O
High
52 SRA_D0/DRD0 I/O
I
53 SRA_D1/DRD1 I/O
I
54 SRA_D2/DRD2 I/O
I
55 SRA_D3/DRD3 I/O
I
O/P
Load
Buffer
Function
200pF
8mA
DSP SRAM Address Line 9/DSP DRAM Address Line 5.
When in SRAM Mode these pins act as the EMI address
line 9. When in DRAM Mode they act as the EMI address
line 5.
100pF
4mA
General-Purpose for DSP1 (Input/Output). Dedicated
general-purpose I/O pin connected to DSP0. Under
control of the GPIODIR and GPIODAT registers inside
the core.
100pF
4mA
General-Purpose for DSP0 (Input/Output). Dedicated
general-purpose I/O pin connected to DSP0. Under
control of the GPIODIR and GPIODAT registers inside
the core.
200pF
8mA
DSP SRAM Address Line 8/DSP DRAM Address Line 4.
When in SRAM Mode these pins act as the EMI address
line 8. When in DRAM Mode they act as the EMI address
line 4.
200pF
8mA
DSP SRAM Address Line 13/DRAM Row Address
Strobe. When in SRAM Mode this pin acts as the EMI
address lines 13. When in DRAM Mode this pin acts as
the row address strobe.
VSS Power Ground.
VDD 3.3V Power Supply.
200pF
8mA
DSP SRAM Write Enable/DRAM Write Enable. This pin
serves as the write enable for the EMI when in DRAM
and SRAM Modes.
200pF
8mA
DSP SRAM Address latch enable/colomn Address. When
in SRAM Mode this pin acts as the EMI Address Latch
Enable. When in DRAM Mode this pin acts as the column
address strobe.
200pF
8mA
DSP SRAM Address Line 12/DSP DRAM Address Line 8.
When in SRAM Mode these pins act as the EMI address
line 12. When in DRAM Mode they act as the EMI
address line 8.
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM
Data Line 0.When in SRAM Mode these pins act as the
EMI multiplexed address and data line 0. When in DRAM
Mode they act as the EMI data line 0.
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM
Data Line 1.When in SRAM Mode these pins act as the
EMI multiplexed address and data line 1. When in DRAM
Mode they act as the EMI data line 1.
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM
Data Line 2.When in SRAM Mode these pins act as the
EMI multiplexed address and data line 2. When in DRAM
Mode they act as the EMI data line 2.
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM
Data Line 3.When in SRAM Mode these pins act as the
EMI multiplexed address and data line 3. When in DRAM
Mode they act as the EMI data line 3.
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