29F128G08CJABA データシートの表示（PDF） - Micron Technology

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29F128G08CJABA

Asynchronous/Synchronous NAND NAND Flash Memory / 52-pad LGA / 48-pin TSOP / 100-ball BGA

Micron Technology 

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32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND

List of Tables

Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9

Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26

Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27

Table 4: Synchronous Interface Mode Selection ............................................................................................. 37

Table 5: Command Set .................................................................................................................................. 48

Table 6: Read ID Parameters for Address 00h ................................................................................................. 53

Table 7: Read ID Parameters for Address 20h .................................................................................................. 53

Table 8: Feature Address Definitions .............................................................................................................. 54

Table 9: Feature Address 01h: Timing Mode ................................................................................................... 56

Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 56

Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 57

Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 57

Table 13: Parameter Page Data Structure ....................................................................................................... 60

Table 14: Status Register Definition ............................................................................................................... 72

Table 15: OTP Area Details ........................................................................................................................... 103

Table 16: Error Management Details ............................................................................................................. 108

Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 109

Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 109

Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 110

Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 110

Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 111

Table 22: Overshoot/Undershoot Parameters ................................................................................................ 112

Table 23: Test Conditions for Input Slew Rate ................................................................................................ 113

Table 24: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 113

Table 25: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 113

Table 26: Test Conditions for Output Slew Rate ............................................................................................. 114

Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 114

Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 114

Table 29: Absolute Maximum Ratings by Device ............................................................................................ 115

Table 30: Recommended Operating Conditions ............................................................................................ 115

Table 31: Valid Blocks per LUN ..................................................................................................................... 115

Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 116

Table 33: Capacitance: 48-Pin TSOP Package ................................................................................................ 116

Table 34: Capacitance: 52-Pad LGA Package .................................................................................................. 116

Table 35: Test Conditions ............................................................................................................................. 117

Table 36: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 117

Table 37: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 118

Table 38: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 118

Table 39: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 119

Table 40: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 119

Table 41: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 121

Table 42: Array Characteristics ..................................................................................................................... 124

PDF: 09005aef836c9ded

Rev. F 12/09 EN

5

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