LTC1647-3 データシートの表示（PDF） - Linear Technology

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LTC1647-3

Dual Hot Swap Controllers

Linear Technology 

LTC1647-1/LTC1647-2/LTC1647-3

APPLICATIO S I FOR ATIO

Power Supply Ramping

VOUT is controlled by placing MOSFET Q1 in the power

path (Figure 1). R1 provides load current fault detection

and R2 prevents MOSFET high frequency oscillation. By

ramping the gate of the pass transistor at a controlled rate

(dV/dt = 10µA/C1), the transient surge current

(I = CLOAD•dV/dt = 10µA•CLOAD/C1) drawn from the main

backplane is limited to a safe value when the board is

inserted into the connector.

When power is first applied to VCC, the GATE pin pulls low.

A low-to-high transition at the ON pin initiates GATE ramp-

up. The rising dV/dt of GATE is set by 10µA/C1 (Figure 5),

where C1 is the total external capacitance between GATE

and GND. The ramp-up time for VOUT is equal to

t = (VCC•C1)/10µA.

VCC + ∆VGATE

VCC

0V

VCC

0V

VGATE

RAMP-UP

SLOPE = 10µA/C1

RAMP-DOWN

SLOPE = –50µA/C1

VOUT

CLOAD DISCHARGES

VON

Figure 5. Supply Turn-On/Off with ON

1647-1/2/3 F05

VCC + ∆VGATE

VCC

0V

VCC

0V

VGATE

VGATE DROOP

DUE TO VCC

RAMP-UP

SLOPE = 10µA/C1

VOUT

FAST RAMP-DOWN

AT UNDERVOLTAGE

LOCKOUT

CLOAD DISCHARGES

OUT OF UVLO

VCC

VLKO

VCC

UNPLUGGED

INTO UVLO

VLKO – VLKH

1647-1/2/3 F06

A high-to-low transition at the ON pin initiates a GATE

ramp-down at a slope of – 50µA/C1. This rate is usually

adequate as the supply bypass capacitors take time to

discharge through the load.

If the ON pin is connected to VCC, or is pulled high before

VCC is first applied, GATE is held low until VCC rises above

the undervoltage lockout threshold, VLKO (Figure 6). Once

the threshold is exceeded, GATE ramps at a controlled rate

of 10µA/C1. When the power supply is disconnected, the

body diode of Q1 holds VCC about 700mV below VOUT. The

GATE voltage droops at a rate determined by VCC. If VCC

drops below VLKO – VLKH, the LTC1647 enters UVLO and

GATE pulls down to GND.

Autoretry

The LTC1647-2 and LTC1647-3 are designed to allow an

automatic reset of the electronic circuit breaker after a

fault condition occurs. This is accomplished by pulling the

ON/FAULT (LTC1647-2) pin or the ON and FAULT pins tied

together (LTC1647-3) high through a resistor, R3, as

shown in Figure 7. An autoretry sequence begins if a fault

occurs. If the circuit breaker trips, FAULT pulls the ON pin

low. After a tRESET interval elapses, FAULT resets and R3

VCC

ON

(5V LOGIC)

FAULT

C3

0.1µF

R1

0.01Ω

Q1

IRF7413

+

R2

10Ω

VOUT

CLOAD

C1

1

8

6

R3

15k

VCC

SENSE GATE

10nF

2

ON/FAULT

4

GND

LTC1647-2

VCC – VSENSE

VGATE

VFAULT

tRESET

tDELAY

tRAMP

1647-1/2/3 F07

Figure 7. Autoretry Sequence

11

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