FDC6301N データシートの表示（PDF） - Fairchild Semiconductor

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FDC6301N

Dual N-Channel , Digital FET

Fairchild Semiconductor 

Electrical Characteristics (TA = 25 OC unless otherwise noted )

Symbol Parameter

Conditions

Min Typ Max Units

OFF CHARACTERISTICS

BVDSS

∆BVDSS/∆TJ

IDSS

Drain-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Zero Gate Voltage Drain Current

IGSS

Gate - Body Leakage Current

ON CHARACTERISTICS (Note 2)

VGS = 0 V, ID = 250 µA

ID = 250 µA, Referenced to 25 o C

25

25

V

mV /oC

VDS = 20 V, VGS = 0 V

1

µA

TJ = 55°C

10

µA

VGS = 8 V, VDS= 0 V

100 nA

∆VGS(th)/∆TJ

VGS(th)

RDS(ON)

Gate Threshold Voltage Temp.Coefficient

Gate Threshold Voltage

Static Drain-Source On-Resistance

ID(ON)

On-State Drain Current

gFS

Forward Transconductance

DYNAMIC CHARACTERISTICS

ID = 250 µA, Referenced to 25 o C

-2.1

VDS = VGS, ID = 250 µA

0.65 0.85

VGS = 2.7 V, ID = 0.2 A

3.8

TJ =125°C

6.3

VGS = 4.5 V, ID = 0.4 A

3.1

VGS = 2.7 V, VDS = 5 V

0.2

VDS = 5 V, ID= 0.4 A

0.25

mV /oC

1.5

V

5

Ω

9

4

A

S

Ciss

Input Capacitance

Coss

Output Capacitance

Crss

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2)

VDS = 10 V, VGS = 0 V,

f = 1.0 MHz

9.5

pF

6

pF

1.3

pF

tD(on)

Turn - On Delay Time

tr

Turn - On Rise Time

VDD = 6 V, ID = 0.5 A,

VGS = 4.5 V, RGEN = 50 Ω

5

10

ns

4.5 10

ns

tD(off)

Turn - Off Delay Time

4

8

ns

tf

Turn - Off Fall Time

3.2

7

ns

Qg

Total Gate Charge

Qgs

Gate-Source Charge

VDS = 5 V, ID = 0.2 A,

VGS = 4.5 V

0.49 0.7 nC

0.22

nC

Qgd

Gate-Drain Charge

0.07

nC

Inverter Electrical Characteristics (TA = 25°C unless otherwise noted)

IO (off)

Zero Input Voltage Output Current

VCC = 20 V, VI = 0 V

1

µA

VI (off)

Input Voltage

VCC = 5 V, IO = 10 µA

0.5

V

VI (on)

VO = 0.3 V, IO = 0.005 A

1

V

RO (on)

Output to Ground Resistance

VI = 2.7 V, IO = 0.2 A

3.8

5

Ω

Notes:

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by

design while RθCA is determined by the user's board design. RθJA shown below for single device operation on FR-4 in still air.

a. 140OC/W on a 0.125 in2 pad of

2oz copper.

b. 180OC/W on a 0.005 in2 of pad

of 2oz copper.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

FDC6301N Rev.D

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