DS2405 データシートの表示（PDF） - Maxim Integrated

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DS2405

Addressable Switch

Maxim Integrated 

DS2405

Skip ROM [CCh]

The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Skip ROM command.

Since the DS2405 contains only the 64-bit ROM with no additional data fields, the Skip ROM is not

applicable and will cause no further activity on the 1-Wire bus if executed. The DS2405 does not interfere

with other 1-Wire parts on a multidrop bus that do respond to a Skip ROM (for example, a DS2405 and

DS1994 on the same bus).

1-WIRE SIGNALING

The DS2405 requires strict protocols to ensure data integrity. The protocol consists of four types of

signaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.

All these signals except Presence Pulse are initiated by the bus master.

The initialization sequence required to begin any communication with the DS2405 is shown in Figure 5.

A Reset Pulse followed by a Presence Pulse indicates the DS2405 is ready to send or receive data given

the correct ROM command.

The bus master transmits (TX) a Reset Pulse (tRSTL, minimum 480μs). The bus master then releases the

line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the 5kΩ pullup resistor.

After detecting the rising edge on the data pin, the DS2405 waits (tPDH, 15-60μs) and then transmits the

Presence Pulse (tPDL, 60-240μs).

INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5

RESISTOR

MASTER

DS2405

480μs ≤ tRSTL < ∞*

480μs ≤ tRSTH < ∞ (includes recovery time)

15μs ≤ tPDH < 60μs

60μs ≤ tPDL < 240μs

∗ In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always

be less than 960μs.

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