LTC1473 データシートの表示（PDF） - Linear Technology

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LTC1473

Dual PowerPath Switch Driver

Linear Technology 

LTC1473

APPLICATIONS INFORMATION

After the transition period, the VGS of both MOSFETs in the

selected switch pair rises to approximately 5.6V. The gate

drive is set at 5.6V to provide ample overdrive for standard

logic-level MOSFET switches without exceeding their

maximum VGS rating.

In the event of a fault condition the current limit loop will

limit the inrush current into the short. At the instant the

MOSFET switch is in current limit, i.e., when the voltage

drop across RSENSE is ±200mV, a fault timer will start

timing. It will continue to time as long as the MOSFET

switch is in current limit. Eventually the preset time will

lapse and the MOSFET switch will latch off. The latch is

reset by deselecting the gate drive input. Fault time-out is

programmed by an external capacitor connected between

the TIMER pin and ground.

POWER PATH SWITCHING CONCEPTS

Power Source Selection

The LTC1473 drives low-loss switches to direct power in

the main power path of a single or dual rechargeable

battery system, the type found in many notebook comput-

ers and other portable equipment.

Figure 3 is a conceptual block diagram that illustrates the

main features of an LTC1473 dual battery power manage-

ment system starting with the three main power sources

and ending at the output load (i.e.: system DC/DC

regulator).

Switches SW A1/B1 and SW A2/B2 direct power from

either batteries to the input of the DC/DC switching regu-

lator. Each of the switches is controlled by a TTL/CMOS

compatible input that can interface directly with a power

management system µP.

Using Tantalum Capacitors

The inrush (and “outrush”) current of the system DC/DC

regulator input capacitor is limited by the LTC1473, i.e.,

the current flowing both in and out of the capacitor during

transitions from one input power source to another is

limited. In many applications, this inrush current limiting

makes it feasible to use smaller tantalum surface mount

capacitors in place of larger aluminum electrolytics.

Note: The capacitor manufacturer should be consulted for

specific inrush current specifications and limitations and

some experimentation may be required to ensure compli-

ance with these limitations under all possible operating

conditions.

Back-to-Back Switch Topology

The simple SPST switches shown in Figure 3 actually

consist of two back-to-back N-channel switches. These

low-loss N-channel switch pairs are housed in 8-pin SO

and SSOP packaging and are available from a number of

manufacturers. The back-to-back topology eliminates the

problems associated with the inherent body diodes in

power MOSFET switches and allows each switch pair to

DCIN

BAT1

BAT2

SW A1/B1

SW A2/B2

INRUSH

CURRENT

LIMITING

+

CIN

OUTPUT LOAD

HIGH

12V

EFFICIENCY

DC/DC

5V

SWITCHING

REGULATOR

3.3V

LTC1473

POWER

MANAGEMENT

µP

1473 F03

Figure 3. LTC1473 PowerPath Conceptual Diagram

8

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