VSC7130RC データシートの表示（PDF） - Vitesse Semiconductor

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VSC7130RC

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

Data Sheet

VSC7130

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Hub Support

Several functions are provided in the CDRx/SDUx circuitry to support FC-AL Hubs. Two programmable

40-bit registers are available to generate data on TX or SO, allowing simple 40-bit patterns to be generated eas-

ily. Monitoring of the serial data out of the repeater provides the user with information concerning data content

of packets as they are received. Many FC-AL ordered sets are detected (all ARBs, IDLE, all LIPs, all CLS and

all OPENs). Furthermore, two 40-bit registers/comparators are provided to allow the user to identify when user

programmable patterns occur in the data. One use of these would be to monitor for the presence of ordered sets

defined after release of this product.

Please refer to the VSC7130 User’s Manual for a more complete description of the ordered set generation

and recognition capabilities and associated register controls.

Performance Monitoring

In order to determine the relative traffic on the link, a 32-bit counter is provided which increments on each

occurrence of an ARB ordered set or an IDLE ordered set. By reading this counter periodically, the relative traf-

fic on the link can be calculated.

Please refer to the VSC7130 User’s Manual for a more complete description of the performance monitoring

capabilities and associated register controls.

Power-On-Reset

The VSC7130 has an internal Power-On-Reset circuit to provide approximately one millisecond delay after

power up during which all Two-Wire accessible registers are reset. An alternate method for resetting the device

is available. If TEST0 and A4 are LOW, the device is reset. Connect an active LOW Reset signal to TEST0 and

A4 if it would be HIGH during normal operation. When the reset input is LOW, the alternative reset method is

activated. When the reset input is HIGH, TEST0 and A4 assume their normal value.

Two-Wire Interface

An industry-standard Two-Wire Interface is provided to allow user access to internal control and status. Use

of the interface is optional. SCL is the serial interface clock running at up to 400kHz when used with readily

available microcontrollers. SDA is a bidirectional data signal. A4 and A3 selects the group address of the device

while A2-A0 set the address. TWI and TWO are used to serially configure the address of daisy-chained devices

in order to accommodate large numbers of devices on each Two-Wire Interface link. INT# is an open drain out-

put used to signal an interruptible event to the microcontroller.

Please refer to the VSC7130 User’s Manual for a more complete description of this interface, including tim-

ing diagrams.

Proprietary Interface

If higher performance than 400kHz is required, a proprietary mode may be used. In this mode, the SCL

clock can operate at a maximum speed of 6.25MHz. Due to the speed of this link, significant electrical limita-

tions may be placed on the link which will restrict trace lengths, the number of daisy-chained devices and the

use of multiple masters.

G52297-0, Rev 4.0

04/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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