VSC7130RC データシートの表示（PDF） - Vitesse Semiconductor

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VSC7130RC

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Data Sheet

VSC7130

Table 2: CDRx Repeater/Retimer Configuration

MODE1 Pin

0

0

1

1

MODE0 Pin

0

1

0

1

T/R Pin

0

1

0

1

n/a

n/a

0

1

CDR1

Repeater (SELRT1=1)

Repeater (SELRT1=1)

Repeater (SELRT1=1)

Repeater (SELRT1=1)

Bypass

Bypass

Retimer (SELRT1=0)

Retimer (SELRT1=0)

CDR0

Repeater (SELRT0=1)

Retimer (SELRT0=0)

Repeater (SELRT0=1)

Retimer (SELRT0=0)

Bypass and power down

Bypass and power down

Repeater (SELRT0=1)

Retimer (SELRT0=0)

The SELRTx signal determines whether the repeater or retimer output is selected, as shown in Figure 4.

The MODEDIS register bit (CHIPCA-01h, bit 7) and the T/RDIS register bit (CHIPCA-01h, bit 4) can be

used to disable the pin controls defined in Table 2 for selecting repeater or retimer mode for each CDR unit. For

CDR0, if the MODEDIS and T/RDIS bits are both set, the ITR0 register bit (CDR0C-20h, bit 4) will control the

repeater/retimer selection. For CDR1, only the MODEDIS register bit needs to be set in order to use ITR1

(CDR1C-28h, bit 4) to control the repeater/retimer selection. A HIGH in ITRx selects repeater mode, and a

LOW selects retimer mode.

Normally, the SI input passes through MUX1 to the input of CDR0 whose output is transmitted on TX+/- if

TXDIS is LOW. If TXDIS is HIGH, TX+ and TX- will be HIGH. Similarly, the RX input normally passes

through MUX2, CDR1 and MUX3 to the SO output.

Retimer Operation

NOTE: Retimer operation is only used for Fibre Channel data at 1.0625Gb/s. Do not use Retimer mode

unless the incoming data is Fibre Channel or follows the Ordered Set structure defined by Fibre Channel. Fail-

ure to do so will result in data corruption.

When CDRx is configured as a Retimer, recovered data is resynchronized to an internally generated baud

rate clock derived from the REFI. This prevents jitter at the inputs from transferring to the outputs. However,

incoming data is not necessarily at the same frequency as the internal baud rate clock, so special Fibre Channel

Ordered Sets, called Fill Words, are added or dropped from the data stream in order to accommodate this speed

difference. The rules for adding and dropping Fill Words are delineated in documents generated by the T11

committee: FC-PH, FC-PH2, FC-PH3, FC-AL, FC-AL2 and FC-AL3. The VSC7130 is compliant with these

rules.

A detailed block diagram of the Retimer is shown in Figure 8. Incoming data goes into a CRU where the

data is recovered and resampled. Recovered data and recovered clock are sent to the Add/Drop FIFO where the

data is stored using the recovered clock. Data is removed from the Add/Drop FIFO and resynchronized by the

Retransmitting Flip-Flop using the internally generated baud rate clock derived from REFI. The output of the

Flip-Flop is recovered serial data which is synchronous to the low-jitter baud rate clock and complies with all

jitter specifications for Fibre Channel.

Page 8

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52297-0, Rev 4.0

04/02/01

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