CXD1961Q データシートの表示（PDF） - Sony Semiconductor

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CXD1961Q

DVB-S Front-end IC (QPSK demodulator + FEC)

Sony Semiconductor 

Fig. 3 QPSK Synchronization monitor

QSYNC Threshold

QSYNC Monitor Period

(QS_N3)×27+(QS_N2)×26+(QS_N1)×25+(QS_N0)×24

256 (fix)

Fig. 4 Costas Loop Filter co-efficiency

Parameter

(0, 0) (0, 1) (1, 0)

(AC2, AC1)

×1

1/2 1/4

(BC2, BC1)

×1

×2

×4

(AK2, AK1)

×1

1/2 1/4

(1, 1)

1/8

×8

1/8

Item

Carrier recovery IIR filter

Carrier recovery tracking range

Clock recovery IIR filter

Fig. 5 Timer period (Sampling Frequency = 60 MHz)

TIMER2

11110000

TIMER1

11001100

TIMER0

10101010

Period (ms)

140 70 35 17.5 8.75 4.38 2.19 1.09

Frequency (kHz) 7.14 14.3 28.6 57.1 114 229 457 914

Fig. 6 V sync monitor period (measurement period counter preset data)

Register

VS_T3 VS_T2 VS_T1 VS_T0

max. : 6656

Period (viterbi clock) ×212

×211

×210

×29

min. : 512

(ex. VS_T (3:0)=(0, 1, 1, 1) → Limit=1×212+0×211+0×210+0×29=4096)

(viterbi clock)

Fig. 7 Clock recovery error data (8 bit) feed back level

NCO

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CE_LEV

(1, 1)

(1, 0)

(0, 1)

(0, 0)

Fig. 8 Bit Error Monitor period (Viterbi clock)

BER_T2

11110000

BER_T1

11001100

BER_T0

10101010

Period

219 218 217 216 215 214 213 26

CXD1961Q

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