MX802 データシートの表示（PDF） - MX-COM Inc

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MX802

DVSR CODEC

MX-COM Inc  

DVSR CODEC

7

MX802

Recommended External Component Notes:

1. Xtal circuitry shown in inset is in accordance with the MX-COM Standard and DBS 800 Crystal

Application Note.

2. External Xtal circuitry is not applicable to the 24-pin/lead version of this device. Only an externally

derived clock input can be used.

3. Functions whose pins are marked with and asterisk (*) in Figure 2 are not available on the 24-pin/lead

versions of this device. Pin numbers illustrated are for 28-pin versions.

4. Table 5 details the actual encoder/decoder sample rates available using the Xtal frequencies

recommended above.

5. Resistor R1 is used as the DBS800 system common pull-up for the C-BUS Interrupt Request IRQ line.

The optimum value will depend on the circuitry connected to the IRQ . Up to 8 peripherals may be

connected to this line.

6. Recommended DRAM parameters:

256kbit x 1 or 1Mbit x 1 Dynamic Random Access Memory with " CAS before RAS" refresh mode.

Maximum Row address time = .200us.

Example DRAM types:

256kbit (262,144 bits)

Texas Instruments (TMS4256-20)

Hitachi (HM51256-15)

1Mbit (1,048,576 bits)

Texas Instruments (TMS4C1024-15)

Hitachi (HM511000-15)

7. Figure 2 shows connections to 4x1 Mbit sections of DRAM. If desired, to simplify PCB layout, the DRAM

inputs A0-A8 may be connected in any order to the MX802 DVSR Codec output pins A0-A8.

Connections to 256kbit DRAM are similar, but A9 I left unconnected.

8. When using the MX802 “stand alone” 9Direct Access), no DRAM sections should be connected.

4 General Description

The MX802 Data/Voice Storage and Retrieval (DVSR) Codec contains a Continuously Variable Slope Delta

Modulation (CVSD) encoder and decoder as well as control and timing circuitry for up to 4Mbits of external

DRAM. As a member of the DBS800 series, it also contains interface and control logic for the “C-BUS” serial

interface.

When used with external DRAM, theMX802 had four primary functions: Speech Storage, Speech layback,

Data Storage, and Data Retrieval. The Speech Storage and Playback may be performed concurrently with

data storage or retrieval.

Speech Storage:

Speech Playback:

Data Storage:

Data Playback:

Speech signals present at the Audio Input may be digitized by the CVSD encoder. The

resulting bit stream is stored in DRAM. This process also provides readings of the

speech signal power level. These readings are used by the system microcontroller for

pause reduction.

Digitized speech may be read from DRAM and converted back into analog from by the

CVSD decoder.

Digital data derived via the C-BUS from the Modem or system data may be stored in

DRAM.

Digital data may be read from DRAM and sent over the C-BUS to the system

microcontroller.

On-chip the Delta Codec is supported by input and output analog switched-capacitor filters and audio output

switching circuitry. The DRAM control and timing circuitry provides all the necessary address, control, and

refresh signals to interface to external DRAM.

The MX802 may also be used without DRAM (as a “stand alone” CVSD Codec), in which case direct access

is provided to the CVSD Codec digital data and clock signals. All signals are controlled by “C-BUS”

commands from the system microcontroller.

1998 MX-COM, Inc.

www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480033.008

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

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