74ABT5074 データシートの表示（PDF） - Philips Electronics
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74ABT5074
Philips Electronics
74ABT5074 Datasheet PDF : 13 Pages
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Philips Semiconductors
Synchronizing dual D-type flip-flop
with metastable immune characteristics
Product data
74ABT5074
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25 °C
MIN
TYP MAX
Tamb = –40 °C to +85 °C
MIN
MAX
VIK
Input clamp voltage
VCC = 4.5 V; IIK = –18 mA
–
–0.9 –1.2
–
VOH
HIGH-level output
voltage
VCC = 4.5 V; IOH = –15 mA;
VI = VIL or VIH
2.5
2.9
–
2.5
VOL
LOW-level output voltage
VCC = 4.5 V; IOL = 20 mA;
VI = VIL or VIH
–
0.35
0.5
–
II
Input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
–
±0.01 ±1.0
–
IOFF Power-off leakage current VCC = 0.0 V; VO or VI v 4.5 V
–
±5.0 ±100
–
IO
Output current1
VCC = 5.5 V; VO = 2.5 V
–50
–75 –180
–50
ICC
Quiescent supply current VCC = 5.5 V; VI = GND or VCC
–
2
50
–
∆ICC
Additional supply current VCC = 5.5 V; one input at 3.4 V,
per input pin2
other inputs at VCC or GND
–
0.25
500
–
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
–1.2
–
0.5
±1.0
±100
–180
50
500
UNIT
V
V
V
µA
µA
mA
µA
µA
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25 °C
VCC = +5.0 V
MIN
TYP MAX
Tamb = –40 °C to +85 °C
VCC = +5.0 V ±0.5 V
MIN
MAX
fmax Maximum clock frequency
1
180
250
–
150
–
tPLH Propagation delay
tPHL CPn to Qn or Qn
1
1.0
2.8
3.9
1.0
4.5
1.0
2.4
3.5
1.0
3.7
tPLH
tPHL
tsk(o)
Propagation delay
SDn, RDn to Qn or Qn
Output skew1, 2
CPn to Qn to Qn
2
1.0
3.5
4.6
1.0
5.5
1.0
3.1
4.2
1.0
4.7
4
–
–
1.5
–
2.0
NOTES:
1. | tPN actual - tPM actual | for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
UNIT
ns
ns
ns
ns
AC SET-UP REQUIREMENTS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
SYMBOL
PARAMETER
WAVEFORM
ts(H)
ts(L)
Set-up time, HIGH or LOW
Dn to CPn
1
th(H)
th(L)
Hold time, HIGH or LOW
Dn to CPn
1
tw (H)
tw (L)
CPn pulse width,
HIGH or LOW
1
tw (L) SDn or RDn pulse width, LOW
2
trec
Recovery time
SDn or RDn to CPn
3
LIMITS
Tamb = +25 °C
VCC = +5.0 V
MIN
TYP
Tamb = –40 °C to +85 °C
VCC = +5.0 V ±0.5 V
MIN
2.5
1.5
2.5
2.5
1.5
2.5
0
–1.4
0
0
–1.4
0
1.5
0.6
1.5
2.4
1.8
2.9
2.0
1.3
2.2
UNIT
ns
ns
ns
ns
2.4
1.3
2.8
ns
2002 Dec 17
6
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