SN74LS290DR2 データシートの表示（PDF） - ON Semiconductor
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SN74LS290DR2 Datasheet PDF : 5 Pages
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SN54/74LS290 D SN54/74LS293
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master / slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1 ⋅ MR2) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 ⋅ MS2) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP1 input must be
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence is
produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
LS293
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous division of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
LS290 MODE SELECTION
RESET/SET INPUTS
OUTPUTS
MR1
H
H
X
L
X
L
X
MR2
H
H
X
X
L
X
L
MS1
L
X
H
L
X
X
L
MS2
X
L
H
X
L
L
X
Q0 Q1 Q2 Q3
L
L
L
L
L
L
L
L
H
L
L
H
Count
Count
Count
Count
LS290
BCD COUNT SEQUENCE
OUTPUT
COUNT
Q0 Q1 Q2 Q3
0
LL
L
L
1
HL
L
L
2
LH
L
L
3
HH
L
L
4
LL
H
L
5
HL
H
L
6
LH H
L
7
HH H
L
8
LL
L
H
9
HL
L
H
NOTE: Output Q0 is connected to Input CP1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
LS293 MODE SELECTION
RESET INPUTS
OUTPUTS
MR1
H
L
H
L
MR2
H
H
L
L
Q0 Q1 Q2 Q3
L
L
L
L
Count
Count
Count
TRUTH TABLE
OUTPUT
COUNT
Q0 Q1 Q2
Q3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
10
L
H
L
H
11
H
H
L
H
12
L
L
H
H
13
H
L
H
H
14
L
H
H
H
15
H
H
H
H
Note: Output Q0 connected to input CP1.
FAST AND LS TTL DATA
5-3
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