74LV259DB(2016) データシートの表示（PDF） - NXP Semiconductors.
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74LV259DB Datasheet PDF : 19 Pages
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NXP Semiconductors
74LV259
8-bit addressable latch
Table 2.
Symbol
Q[0:7]
D
LE
MR
VCC
Pin description …continued
Pin
4, 5, 6, 7, 9, 10, 11, 12
13
14
15
16
6. Functional description
Description
latch output
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
Table 3. Mode select table
H = HIGH voltage level; L = LOW voltage level
LE
MR
L
H
H
H
L
L
H
L
Mode
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the
LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared
Operating modes Input
Output
MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
master reset
L H XX X X L
L
L
L
L
L
L
L
demultiplex (active L L d L L L Q = d L
L
L
L
L
L
L
HIGH) decoder
L L dH L L L
Q=d L
L
L
L
L
L
(when D = H)
L L dL H L L
L
Q=d L
L
L
L
L
L L dH H L L
L
L
Q=d L
L
L
L
L L dL L H L
L
L
L
Q=d L
L
L
L L dH L H L
L
L
L
L
Q=d
L
L L dL H H L
L
L
L
L
L
Q=d L
L L dH H H L
L
L
L
L
L
L
Q=d
store (do nothing) H H X X X X q0
q1
q2
q3
q4
q5 q6 q7
addressable latch H L d L L L
Q = d q1
q2
q3
q4
q5 q6 q7
H
L dH L L
q0
Q = d q2
q3
q4
q5 q6
q7
H L dL H L
q0
q1
Q = d q3
q4
q5 q6 q7
H L dH H L
q0
q1
q2
Q = d q4
q5 q6 q7
H L d L L H q0
q1
q2
q3
Q = d q5 q6 q7
H L d H L H q0
q1
q2
q3
q4
Q = d q6 q7
H L d L H H q0
q1
q2
q3
q4
q5 Q = d q7
H L H H H H q0
q1
q2
q3
q4
q5 q6 Q = d
74LV259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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