74LVC821ABQ データシートの表示（PDF） - Unspecified
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74LVC821ABQ
Unspecified
74LVC821ABQ Datasheet PDF : 20 Pages
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Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
[1] All typical values are measured Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
11. Dynamic characteristics
Table 8: Dynamic characteristics
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10
Symbol Parameter
Conditions
Min
Tamb = −40 °C to +85 °C [1]
tPHL, tPLH propagation delay CP to Qn
see Figure 7
VCC = 1.2 V
-
tPZH, tPZL 3-state output enable time OE to Qn
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 9
1.5
[2] 1.5
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
-
1.5
[2] 1.3
tPHZ, tPLZ 3-state output disable time OE to Qn
see Figure 9
VCC = 1.2 V
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
1.5
[2] 1.5
tW
clock pulse width HIGH or LOW
see Figure 7
VCC = 1.2 V
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
3.3
[2] 3.3
tsu
set-up time Dn to CP
see Figure 8
VCC = 1.2 V
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
0.9
[2] 1.9
th
hold time Dn to CP
see Figure 8
fmax
maximum clock frequency
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 to 3.6 V
see Figure 7
-
1.5
[2] 1.5
VCC = 1.2 V
-
tsk(0)
CPD
skew
power dissipation capacitance per gate
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V
150
[2] 150
[3] -
[4] [5]
outputs enabled
-
outputs disabled
-
Typ
Max Unit
18
-
-
8.5
3.7
7.3
20
-
-
8.8
3.5
7.6
9.0
-
-
6.8
3.0
6.2
-
-
-
-
1.7
-
-
-
-
-
0.6
-
-
-
-
-
0.0
-
-
-
-
-
200
-
-
1.0
17
-
11
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
pF
pF
9397 750 13276
Product data sheet
Rev. 03 — 11 May 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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