74VHC4040MTC データシートの表示（PDF） - Fairchild Semiconductor

部品番号

コンポーネント説明

メーカー

74VHC4040MTC

12-Stage Binary Counter

Fairchild Semiconductor 

August 1993

Revised April 1999

74VHC4040

12-Stage Binary Counter

General Description

The VHC4040 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It achieves

the high-speed operation similar to equivalent Bipolar

Schottky TTL while maintaining the CMOS low power dissi-

pation. The VHC4040 is a 12-stage counter which incre-

ments on the negative edge of the input clock and all

outputs are reset to a low level by applying a logical high

on the reset input. An input protection circuit insures that

0V to 7V can be applied to the inputs without regard to the

supply voltage. This device can be used to interface 5V to

3V systems and two supply systems such as battery

backup. This circuit prevents device destruction due to mis-

matched supply and input voltages.

Features

s High speed; fMAX = 210 MHz at VCC = 5V

s Low power dissipation: ICC = 4 µA (max) at TA = 25°C

s High noise immunity: VNIH =VNIL = 28% VCC (min)

s Power down protection is provided on all inputs

s Wide operating voltage range: VCC (opr) = 2V − 5.5V

s Low noise: VOLP = 0.8V (max)

s Pin and function compatible with 74HC4040

Ordering Code:

Order Number Package Number

Package Description

74VHC4040M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC4040MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC4040N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Q0–Q11

CP

MR

Description

Flip-Flop Outputs

Negative Edged Triggered Clock

Master Reset

© 1999 Fairchild Semiconductor Corporation DS011641.prf

www.fairchildsemi.com

Share Link: