74VHCT74AN データシートの表示（PDF） - Fairchild Semiconductor
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74VHCT74AN Datasheet PDF : 6 Pages
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July 1997
Revised April 1999
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHCT74A is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D INPUT
is transferred to the Q OUTPUT during the positive going
transition of the CK pulse. CLR and PR are independent of
the CK and are accomplished by setting the appropriate
input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC = 0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Features
s High speed: fMAX = 160 MHz (typ) at TA = 25°C
s High noise immunity: VIH = 2.0V, VIL = 0.8V
s Power down protection is provided on all inputs and
outputs
s Low power dissipation:
ICC = 2 µA (max) at TA = 25°C
s Pin and function compatible with 74HCT74
Ordering Code:
Order Number Package Number
Package Description
74VHCT74AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHCT74ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT74AMTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D1, D2
CK1, CK2
CLR1, CLR2
PR1, PR2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Outputs
Truth Table
Inputs
Outputs
Function
CLR PR D CK Q Q
L
HX X
L H Clear
H L X X H L Preset
L
H
H
H
L
H
H
H
X
L
H
X
X
HH
LH
HL
Qn Qn No
Change
© 1999 Fairchild Semiconductor Corporation DS500026.prf
www.fairchildsemi.com
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