9LPRS525 データシートの表示（PDF） - Integrated Device Technology
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9LPRS525 Datasheet PDF : 21 Pages
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ICS9LPRS525
PC MAIN CLOCK
Table 1: CPU Frequency Select Table
FSLC2 FSLB1 FSLA1
B0b7 B0b6 B0b5
CPU
MHz
SRC PCI REF USB DOT
MHz MHz MHz MHz MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66 100.00 33.33 14.318 48.00 96.00
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6)
B1b4 B1b3 B1b2 B1b1 Pin 17 Pin 18
MHz MHz
Spread
%
Comment
0
0
00
PLL 3 disabled
0
0
0 1 100.00 100.00 0.5% Down Spread
SRC clocks from SRC_MAIN
0
0
1 0 100.00 100.00 0.5% Down Spread
Only SRCCLK1 from PLL3
0
0
1 1 100.00 100.00 1% Down Spread
Only SRCCLK1 from PLL3
0
1
0 0 100.00 100.00 1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0 1 100.00 100.00 2% Down Spread
Only SRCCLK1 from PLL3
0
1
1 0 100.00 100.00 2.5% Down Spread
Only SRCCLK1 from PLL3
0
1
1 1 N/A N/A
N/A
N/A
1
0
0 0 24.576 24.576
None
24.576Mhz on SE1 and SE2
1
0
0 1 24.576 98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
1
0
1 0 98.304 98.304
None
98.304Mhz on SE1 and SE2
1
0
1 1 27.000 27.000
None
27Mhz on SE1 and SE2
1
1
0 0 25.000 25.000
None
25Mhz on SE1 and SE2
1
1
0 1 N/A N/A
N/A
N/A
1
1
1 0 N/A N/A
N/A
N/A
1
1
1 1 N/A N/A
N/A
N/A
IDTTM PC MAIN CLOCK
10
1484B—01/21/10
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