A64E06161(2004) データシートの表示（PDF） - AMIC Technology

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A64E06161
(Rev.:2004)

1M X 16 Bit Low Voltage Super RAM

AMIC Technology 

A64E06161

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol

CIN*

CI/O*

Parameter

Input Capacitance

Input/Output Capacitance

Min.

Max.

Unit

-

6

pF

-

6

pF

* These parameters are sampled and not 100% tested.

Conditions

VIN = 0V

VI/O = 0V

Initialization

The A64E06161 is initialized in the power-on sequence according to the following.

1. To stabilize internal circuits, after turning on the power, a 200µs or longer wait time must precede any signal toggling.

2. After the wait time, it can be normal operation.

Power on Chart

VCC(min)

VCC

CE

200us

Wait Time

ZZ

Normal Operation

Notes: 1. Following power application, make CE high level during the wait time 200us interval.

2. After power on sequence, the normal operating ZZ must keep at high.

Standby Mode State Machines

Power On

Wait 200us

CE = VIH

Initial State

CE = VIH, ZZ = VIH

CE = VIL

ZZ = VIH

Standny Mode

CE = VIL, ZZ = VIH

HB or/and LB = VIL

Active Mode

CE = VIH, ZZ = VIL

CE = VIH

ZZ = VIH

CE = VIH

ZZ = VIL

CE = VIH, ZZ = VIH

CE = VIH, ZZ = VIL

CE = VIL

ZZ = VIH

PAR Mode

(12M/8M/4M bits)

DPD Mode

(Data Invalid)

CE = VIH, ZZ = VIL

Note: DPD is enable when CR register A4 is “0”; otherwise, PAR is enable.

PRELIMINARY (November, 2004, Version 0.1)

5

AMIC Technology, Corp.

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