AD10242TZ/883B(RevD) データシートの表示（PDF） - Analog Devices
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AD10242TZ/883B
(Rev.:RevD)
(Rev.:RevD)
Analog Devices
AD10242TZ/883B Datasheet PDF : 16 Pages
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AD10242
Parameter
Temp
Test
Level
Mil
Subgroup
AD10242BZ/TZ
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE9
Analog Input @ 1.2 MHz
25°C
I
@ 4.85 MHz
25°C
I
4
Full
II
5, 6
@ 9.9 MHz
25°C
I
4
Full
II
5, 6
@ 19.5 MHz
25°C
I
4
Full
II
5, 6
81
70
80
70
79
63
70
63
69
60
67
60
66
TWO-TONE IMD REJECTION10
F1, F2 @ –7 dBFS
Full
II
4, 5, 6
70
76
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
CHANNEL-TO-CHANNEL ISOLATION11 25°C
IV
12
75
80
dB
TRANSIENT RESPONSE
25°C
V
10
ns
LINEARITY
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
(Encode = 20 MHz)
25°C
IV
12
Full
IV
12
25°C
V
Full
V
0.3
1.0
LSB
0.5
1.25 LSB
0.3
LSB
0.5
LSB
OVERVOLTAGE RECOVERY TIME12
VIN = 2.0 × FS
Full
VIN = 4.0 × FS
Full
DIGITAL OUTPUTS
Logic Compatibility
Logic “1” Voltage13
Full
Logic “0” Voltage14
Full
Output Coding
IV
12
IV
12
I
1, 2, 3
I
1, 2, 3
50
100 ns
75
200 ns
CMOS
3.5
4.2
V
0.45
0.65 V
Twos Complement
POWER SUPPLY
AVCC Supply Voltage
Full
I (AVCC) Current
Full
AVEE Supply Voltage
Full
I (AVEE) Current
Full
DVCC Supply Voltage
Full
I (DVCC) Current
Full
ICC (Total) Supply Current
Full
Power Dissipation (Total)
Full
Power Supply Rejection Ratio (PSRR)
Full
Pass-Band Ripple to 10 MHz
Full
VI
V
VI
V
VI
V
I
1, 2, 3
I
1, 2, 3
I
7, 8
IV
12
5.0
V
260
mA
–5.0
V
55
mA
5.0
V
25
mA
350
400 mA
1.75
2.0
W
0.01
0.02 % FSR/% VS
0.2 dB
NOTES
1Gain tests are performed on AIN3 over specified input voltage range.
2Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.
3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.
5ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details.
6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS.
8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
10Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz
± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz.
11Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A IN1).
12Input driven to 2× and 4× AIN1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed.
13Outputs are sourcing 10 µA.
14Outputs are sinking 10 µA.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. D
–3–
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