AD7224KN データシートの表示（PDF） - Analog Devices
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AD7224KN Datasheet PDF : 8 Pages
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AD7224
Table I. AD7224 Truth Table
RESET LDAC WR CS Function
H
L
L L Both Registers are Transparent
H
X
H X Both Registers are Latched
H
H
X H Both Registers are Latched
H
H
L L Input Register Transparent
H
H
g L Input Register Latched
H
L
L H DAC Register Transparent
H
L
g H DAC Register Latched
L
X
X X Both Registers Loaded
With All Zeros
g
H
H H Both Register Latched With All Zeros
and Output Remains at Zero
g
L
L L Both Registers are Transparent and
Output Follows Input Data
H = High State, L = Low State, X = Don’t Care.
All control inputs are level triggered.
The contents of both registers are reset by a low level on the
RESET line. With both registers transparent, the RESET line
functions like a zero override with the output brought to 0 V for
the duration of the RESET pulse. If both registers are latched, a
“LOW” pulse on RESET will latch all 0s into the registers and
the output remains at 0 V after the RESET line has returned
“HIGH”. The RESET line can be used to ensure power-up to
0 V on the AD7224 output and is also useful, when used as a
zero override, in system calibration cycles. Figure 3 shows the
input control logic for the AD7224.
LDAC
WR
CS
RESET
DAC
REGISTER
INPUT
REGISTER
INPUT DATA
Figure 3. Input Control Logic
CS
t1
t3
WR
t2
t4
t2
LDAC
DATA
IN
t5 t6
DATA
VALID
t3
t1
t4
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD.
tr = tf = 20ns OVER VDD RANGE
2. TIMING MEASUREMENT REFERENCE LEVEL IS
VINH + VINL
2
Figure 4. Write Cycle Timing Diagram
SPECIFICATION RANGES
For the DAC to maintain specified accuracy, the reference volt-
age must be at least 4 V below the VDD power supply voltage.
This voltage differential is required for correct generation of bias
voltages for the DAC switches.
With dual supply operation, the AD7224 has an extended VDD
range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to
+16.5 V). Operation is also specified for a single VDD power
supply of +15 V ± 5%.
Performance is specified over a wide range of reference voltages
from 2 V to (VDD – 4 V) with dual supplies. This allows a range
of standard reference generators to be used such as the AD580,
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that in order to achieve an output voltage range
of 0 V to +10 V, a nominal +15 V ± 5% power supply voltage is
required by the AD7224.
GROUND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. This is especially true in micropro-
cessor systems where digital noise is prevalent. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7224. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7224 AGND and
DGND pins (IN914 or equivalent).
Applying the AD7224
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7224, with the
output voltage having the same positive polarity as VREF. The
AD7224 can be operated single supply (VSS = AGND) or with
positive/negative supplies (see op-amp section which outlines
the advantages of having negative VSS). Connections for the uni-
polar output operation are shown in Figure 5. The voltage at
VREF must never be negative with respect to DGND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. The code table for unipolar output
operation is shown in Table II.
DB7
DATA
(8-BIT)
DB0
CS
WR
LDAC
RESET
VREF
3
VDD
DAC
AD7224
VOUT
VSS
AGND
DGND
Figure 5. Unipolar Output Circuit
Table III. Unipolar Code Table
DAC Register Contents
MSB
LSB
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
Analog Output
+V
REF
255
256
+V
REF
129
256
+V REF
128
256
=
+
V
REF
2
+V
REF
127
256
+V
REF
1
256
0000 0000
0V
( )( ) Note: 1 LSB = V REF
2−8
=
V
REF
1
256
–6–
REV. B
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