EVAL-AD7484CB データシートの表示（PDF） - Analog Devices

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EVAL-AD7484CB

3MSPS, 14-Bit SAR ADC

Analog Devices 

Pin

Mnemonic

AVDD

CBIAS

AGND

VIN

VREF1

VREF2

VREF3

STBY

NAP

DVDD

DGND

VDRIVE

CONVST

RESET

MODE2

MODE1

CLIP

CS

RD

WRITE

BUSY

D0 - D13

D14

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTION

AD7484

Description

Positive power supply for analog circuitry.

Decoupling pin for internal bias voltage. A 100nF capacitor should be placed between this pin and

AGND.

Power supply ground for analog circuitry.

Analog input. Single-ended analog input channel.

Reference Output. VREF1 connects to the output of the internal 2.5V reference. A 1µF capacitor must

be placed between this pin and AGND.

Reference Input. A 1µF capacitor must be placed between this pin and AGND. When using an external

voltage reference source, the reference voltage should be applied to this pin.

Reference decoupling pin. When using the internal reference, a 100nF must be connected from this pin

to AGND. When using an external reference source, this pin should be connected directly to AGND.

Standby logic input. When this pin is logic high, the device will be placed in Standby mode. See Power

Saving Section for further details.

Nap logic input. When this pin is logic high, the device will be placed in a very low power mode. See

Power Saving Section for further details.

Positive power supply for digital circuitry.

Ground reference for digital circuitry.

Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage

the interface logic of the AD7484 will operate.

Convert Start Logic Input. A conversion is initiated on the falling edge of CONVST signal. The input

track/hold amplifier goes from track mode to hold mode and the conversion process commences.

Reset Logic Input. A logic 0 on this pin resets the internal state machine and terminates a conversion

that may be in progress. Holding this pin low keeps the part in a reset state.

Operating Mode Logic Input. See Table 3 for details.

Operating Mode Logic Input. See Table 3 for details.

Logic input. A logic high on this pin enables output clipping. In this mode, any input voltage that is

greater than positive full scale or less than negative full scale will be clipped to all 1’s or all 0’s

respectively. Further details are given in the Offset / Overrange setion.

Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The

data bus is brought out of tri-state and the current contents of the output register driven onto the data

lines following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to

perform a write to the Offset Register. CS can be hardwired permanently low.

Read Logic Input. Used in conjunction with CS to access the conversion result.

Write Logic Input. Used in conjunction with CS to write data to the Offset Register. When the desired

offset word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling

edge of this pulse which latches in the word into the Offset Register.

Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low

after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 2,

the BUSY signal returns high when the conversion result has been clocked into the output register. In

Parallel Mode 1, the BUSY signal returns high as soon as the conversion has been completed but the

conversion result does not get clocked into the output register until the falling edge of the next

CONVST pulse.

Data I/O Bits (D13 is MSB). These are tri-state pins that are controlled by CS, RD and WRITE.

The operating voltage level for these pins is determined by the VDRIVE input.

Data Output Bit for overranging. If the over range feature is not used, this pin should be pulled to

DGND via a 100k⍀ resistor.

REV. PrC 7/13/01

–5–

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