EVAL-AD7484CB データシートの表示（PDF） - Analog Devices

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EVAL-AD7484CB

3MSPS, 14-Bit SAR ADC

Analog Devices 

PRELIMINARY TECHNICAL DATA

AD7484

CIRCUIT DESCRIPTION

CONVERTER OPERATION

The AD7484 is a 14-bit error correcting successive ap-

proximation analog-to-digital converter based around a

capacitive DAC. It provides the user with track/hold, refer-

ence, A/D converter and versatile interface logic functions

on a single chip. The normal analog input signal range that

the AD7484 can convert is 0 to 2.5 Volts. By using the

offset and overrange features on the ADC, the AD7484 can

convert analog input signals from -200mV to +2.7V while

operating from a single +5V supply. The part requires a

+2.5V reference which can be provided from the part’s own

internal reference or an external reference source. Figure 1

shows a very simplified schematic of the ADC. The Control

Logic, SAR and the Capacitive DAC are used to add and

subtract fixed amounts of charge from the sampling capaci-

tor to bring the comparator back to a balanced condition.

CAPACITIVE

DAC

COMPARATOR

VIN

VREF

SWITCHES

SAR

CONTROL

INPUTS

CONTROL LOGIC

OUTPUT DATA

14-BIT PARALLEL

Figure 1. Simplified Block Diagram of AD7484

Conversion is initiated on the AD7484 by pulsing the

CONVST input. On the falling edge of CONVST, the

track/hold goes from track to hold mode and the conversion

sequence is started. Conversion time for the part is TBD

nS. Figure 2 shows the ADC during conversion. When

conversion starts, SW2 will open and SW1 will move to

position B causing the comparator to become unbalanced.

The ADC then runs through its successive approximation

routine and brings the comparator back into a balanced

condition. When the comparator is rebalanced, the conver-

sion result is available in the SAR register.

At the end of conversion, the track/hold returns to track-

ing mode and the acquisition time begins. The track/hold

acquisition time is TBD nS. Figure 3 shows the ADC

during its acquistition phase. SW2 is closed and SW1 is

in position A. The comparator is held in a balanced con-

dition and the sampling capacitor acquires the signal on

VIN.

CAPACITIVE

DAC

A

VIN

SW1 B

AGND

SW2

+

-

COMPARATOR

CONTROL LOGIC

Figure 3. ADC Acquisition Phase

ADC TRANSFER FUNCTION

The output coding of the AD7484 is straight binary. The

designed code transitions occur midway between successive

integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, etc.). The

LSB size is VREF / 16384. The nominal transfer characteris-

tic for the AD7484 in shown in figure 4 below. This

transfer characteristic may be shifted as detailed in the Off-

set/Overrange section.

111...111

111...110

111...000

011...111

1LSB = VREF/16384

000...010

000...001

000...000

0V 0.5LSB

+VREF-1.5LSB

ANALOG INPUT

Figure 4. AD7484 Transfer Characteristic

CAPACITIVE

DAC

A

VIN

SW1 B

AGND

SW2

+

-

COMPARATOR

CONTROL LOGIC

Figure 2. ADC Conversion Phase

REV. PrC 7/13/01

–7–

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