ADP3208C データシートの表示（PDF） - ON Semiconductor
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ADP3208C Datasheet PDF : 37 Pages
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ADP3208C
ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1
= PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise
noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min Typ Max Unit
CURRENT MONITOR
Current Gain Accuracy
IMON/ILIM
Measured from ILIMP to IMON
ILIM = −20 mA
ILIM = −10 mA
ILIM = −5 mA
IMON Clamp Voltage
VMAXMON
Relative to FBRTN, ILIMP = −30 mA
PULSE WIDTH MODULATOR − Clock Oscillator
9.5
10
10.5
9.3
10
10.7
9.0
10
11.0
1.0
1.05
V
RT Voltage
PWM Clock Frequency
Range (Note 2)
VRT
VARFREQ = High, RT = 125 kW,
1.22 1.25 1.27
V
VVID = 1.5000 V
VARFREQ = Low, See also VRT(VVID) formula 0.98
1.0
1.02
fCLK
Operating Range
0.3
3.0
MHz
PWM Clock Frequency
RAMP GENERATOR
fCLK
TA = 25°C, VVID = 1.2000 V
RT = 73 kW
RT = 125 kW
RT = 180 kW
kHz
1200 1470 1720
680
920 1120
400
640
840
RAMP Voltage
RAMP Current Range
(Note 2)
VRAMP
IRAMP
EN = high, IRAMP = 30 mA
EN = low
EN = high
EN = low, RAMP = 19 V
0.9
1.0
1.1
V
VIN
1.0
100
mA
−0.5
+0.5
PWM COMPARATOR
PWM Comparator Offset
(Note 2)
VOSRPM
VRAMP − VCOMP
−3.0
3.0
mV
RPM COMPARATOR
RPM Current
RPM Comparator Offset
(Note 2)
IRPM
VVID = 1.2 V, RT = 125 kW,
−8.8
mA
VARFREQ = High, See also IRPM(RT) formula
VOSRPM
VCOMP − (1 +VRPM)
−3.0
3.0
mV
EPWM CLOCK SYNC
Trigger Threshold (Note 2)
Relative to COMP sampled TCLK earlier
2−phase configuration
1−phase configuration
mV
400
450
SWITCH AMPLIFIER
SW Common Mode Range
(Note 2)
VSW(X)CM
Operating Range for current sensing
−600
+200 mV
SW Resistance
RSW_PGND(X) Measured from SW to PGND
ZERO CURRENT SWITCHING COMPARATOR
3.0
kW
SW ZCS Threshold
Masked Off Time
VDCM(SW1)
tOFFMSKD
DCM mode, DPRSLP = 3.3 V
Measured from DRVH neg edge to DRVH
pos edge at max frequency of operation
−6.0
mV
700
ns
SYSTEM I/O BUFFERS VID[6:0], PSI INPUTS
Input Voltage
Input Current
VID Delay Time (Note 2)
Refers to driving signal level
Logic low, Isink w 1 mA
Logic high, Isource v −5 mA
V
0.3
0.7
V = 0.2 V
mA
VID[6:0], DPRSLP (active pulldown to GND)
−1.0
PSI (active pullup to VCC)
+1.0
Any VID edge to FB change 10%
200
ns
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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