EVAL-ADT7461EB データシートの表示（PDF） - Analog Devices

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EVAL-ADT7461EB

±1°C Temperature Monitor with Series Resistance Cancellation

Analog Devices 

ADT7461

SMBus TIMING SPECIFICATIONS

Table 2. SMBus Timing Specifications1

Parameter

Limit at TMIN and TMAX

fSCLK

400

tLOW

1.3

tHIGH

0.6

tR

300

tF

300

tSU; STA

600

tHD; STA2

600

t3

SU; DAT

100

tHD; DAT

300

tSU; STO4

600

tBUF

1.3

Unit

kHz max

µs min

µs min

ns max

ns max

ns min

ns min

ns min

ns min

ns min

µs min

1 Guaranteed by design, but not production tested.

2 Time from 10% of SDATA to 90% of SCLK.

3 Time for 10% or 90% of SDATA to 10% of SCLK.

4 Time for 90% of SCLK to 10% of SDATA.

Description

Clock low period, between 10% points

Clock high period, between 90% points

Clock/data rise time

Clock/data fall time

Start condition setup time

Start condition hold time

Data setup time

Data hold time

Stop condition setup time

Bus bree time between stop and start conditions

SCLK

SDATA

tBUF

STOP START

tLOW

tR

tHD;STA

tHD;DAT

tF

tHIGH

tSU;DAT

tHD;STA

tSU;STA

START

Figure 2. Serial Bus Timing

tSU;STO

STOP

Rev. A | Page 4 of 24

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